Delay analysis of sub-path on fabricated chips by several path-delay tests

Abstract

We propose a method to analysis the delay of the sub-path on fabricated chips by the several path-delay tests. In recent years, the process variation causes the timing faults. To detect the faults, the path-delay test is one of the most promising methods. The path-delay test checks whether the signals along the target paths in fabricated LSIs are propagated under the specified frequency. In this paper, we propose a method to analysis the delay value of the paths with path-delay tests. The proposed method consists of 1) path-delay tests for several paths, 2) estimation of the sub-path of the testing paths, and 3) expansion of the remaining path according to the resultant estimations. We confirm that our proposed method calculates the delay with about 0.05% errors empirically.