Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

Mnejja, Sirine; Aydi, Yassine; Abid, Mohamed; Monteleone, Salvatore; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide

doi:10.3390/electronics9060913

Cited by 7 publications

(5 citation statements)

References 33 publications

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“…[46], while a communication-on-chip system focused on topology reconfiguration has been advanced in ref. [47].…”

Section: Related Workmentioning

confidence: 99%

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Aydi,

Mnejja,

Mohammed

et al. 2023

Applied Sciences

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In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

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“…[46], while a communication-on-chip system focused on topology reconfiguration has been advanced in ref. [47].…”

Section: Related Workmentioning

confidence: 99%

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Aydi,

Mnejja,

Mohammed

et al. 2023

Applied Sciences

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, trade-offs with respect to cost and hardware complexity should be spelt out. The integration of MINs as an underlay/backbone for wireless network-on-chip communication has just begun to receive attention for improving the network performance (see [76]). It is expected that more architectures would be adapted to network-on-chip (NOC) communication in the future.…”

Section: Deadlock Avoidancementioning

confidence: 99%

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

et al. 2021

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Interconnection networks provide an effective means by which components of a system such as processors and memory modules communicate to provide reliable connectivity. This facilitates the realization of a highly efficient network design suitable for computational-intensive applications. Particularly, the use of multistage interconnection networks has unique advantages as the addition of extra stages helps to improve the network performance. However, this comes with challenges and trade-offs, which motivates researchers to explore various design options and architectural models to improve on its performance. A particular class of these networks is shuffle exchange network (SEN) which involves a symmetric N-input and N-output architecture built in stages of N/2 switching elements each. This paper presents recent advances in multistage interconnection networks with emphasis on SENs while discussing pertinent issues related to its design aspects, and taking lessons from the past and current literature. To achieve this objective, applications, motivating factors, architectures, shuffle exchange networks, and some of the performance evaluation techniques as well as their merits and demerits are discussed. Then, to capture the latest research trends in this area not covered in contemporary literature, this paper reviews very recent advancements in shuffle exchange multistage interconnection networks within the last few years and provides design guidelines as well as recommendations for future consideration.

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“…is the set of edges of graph G. The edge of graph G is a pair of arbitrary two nodes, v and w of V(G). The necessary and sufficient condition for the existence of an edge (v, w) is the presence of a communication link between nodes v and w [10][11][12][13][14][15].…”

Section: Related Workmentioning

confidence: 99%

A Novel Interconnection Network with Improved Network Cost Through Shuffle-Exchange Permutation Graph

et al. 2021

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The interconnection network represents an interconnected structure of processors that strongly determines the performance quality of a parallel processing system. The shuffle-exchange permutation (SEP) network with three degrees has high fault tolerance and can be efficiently simulated through star, bubble-sort, and pancake graphs. This study proposes a new interconnection network: the new SEP (NSEP), which improves the diameter and reduces network cost by adding one edge to the SEP network, and presents its graph properties and routing algorithms. The NSEP network, with a degree of connectivity of four, demonstrated maximum fault tolerance and Hamiltonian cycle. Furthermore, the diameter was seen to be improved by 40% or more and the network cost by 20% or more.

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Delta Multi-Stage Interconnection Networks for Scalable Wireless On-Chip Communication

Cited by 7 publications

References 33 publications

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

A Novel Interconnection Network with Improved Network Cost Through Shuffle-Exchange Permutation Graph

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