Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

Chen, Z.X.; Yu, Hao; Singh, Navaneet Kumar; Shen, Nan; Sayanthan, R.D.; Lo, G. Q.; Kwong, Dim‐Lee

doi:10.1109/led.2009.2021079

Cited by 191 publications

(88 citation statements)

References 19 publications

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“…However, the low ON-state current in Si TFETs, due to poor band-to-band tunneling efficiency, is a major challenge to be overcome. This problem is being extensively studied using strain, hetero-structures, low bandgap materials, high-k gate insulators and nanowires [6,[11][12][13][14]. The other problem with the TFET is that in aggressively scaled devices, random variability in transistor performance due to random dopant fluctuations (RDF) can become significant [15].…”

Section: Introductionmentioning

confidence: 99%

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Kumar

Janardhanan

2013

IEEE Trans. Electron Devices

563

249

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Abstract-Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Further, fabrication of doping-less TFET does not require high-temperature doping/annealing processes and therefore, cuts down the thermal budget opening up the possibilities for fabricating TFETs on single crystal silicon-onglass substrates formed by wafer scale epitaxial transfer.

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Section: Introductionmentioning

confidence: 99%

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Kumar

Janardhanan

2013

IEEE Trans. Electron Devices

563

249

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“…Vertical channel TFETs are relatively easy to fabricate. Vertical nanowires with a cylindrical shape can be grown with a metal nanoparticle as a catalyst [18], or etched (and oxidized) using a patterned mask [19][20][21]. The vertical nanowires can be turned into nanowire TFETs by forming the drain, gate electrode, and source.…”

Section: Cylindrical Nanowire Channelmentioning

confidence: 99%

Tunneling Field-Effect Transistors for Ultra-Low-Power Application

Park

2015

Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting

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One of the major roadblocks to further scaling of complementary metaloxide semiconductor (CMOS) devices is power consumption. Reduction of power consumption requires low operation voltage, which requires low threshold voltage. In order to decrease the threshold voltage without excessive increase of OFF current, reduction of the subthreshold swing is essential. To reduce the subthreshold swing, various carrier injection mechanisms other than thermal carrier injection have been proposed. Currently, interband tunneling is the most promising mechanism and the device that utilizes such a mechanism is a tunneling field-effect transistor (TFET). After the introduction to the fundamentals of TFETs, various approaches to increase the drain current of Si TFETs by device structure engineering are described. The last section focuses on bandgap engineering to enhance the drain current of TFETs.

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“…One of such devices is the TFET [22][23][24][25][26][27][28]. Unlike the MOSFET, which utilizes thermionic injection of carriers, TFET uses tunneling as the carrier injection mechanism.…”

Section: Drainmentioning

confidence: 99%

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Kwong

Sun

et al. 2012

Journal of Nanotechnology

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This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.

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Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

Cited by 191 publications

References 19 publications

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Tunneling Field-Effect Transistors for Ultra-Low-Power Application

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

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