Demystifying Soft Error Assessment Strategies on ARM CPUs: Microarchitectural Fault Injection vs. Neutron Beam Experiments

Chatzidimitriou, Athanasios; Bodmann, Pablo; Papadimitriou, George; Gizopoulos, Dimitris; Rech, Paolo

doi:10.1109/dsn.2019.00018

Cited by 43 publications

(27 citation statements)

References 56 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, it takes lots of time to inject faults even though RTL models become available. Lastly, SFI cannot provide precise fault coverage against soft errors as it is challenging to mimic realistic soft errors by intentional fault injection campaigns [40].…”

Section: Discussionmentioning

confidence: 99%

Survey of Software-Implemented Soft Error Protection

2022

Electronics

View full text Add to dashboard Cite

As soft errors are important design concerns in embedded systems, several schemes have been presented to protect embedded systems against them. Embedded systems can be protected by hardware redundancy; however, hardware-based protections cannot provide flexible protection due to hardware-only protection modifications. Further, they incur significant overheads in terms of area, performance, and power consumption. Therefore, hardware redundancy techniques are not appropriate for resource-constrained embedded systems. On the other hand, software-based protection techniques can be an attractive alternative to protect embedded systems, especially specific-purpose architectures. This manuscript categorizes and compares software-based redundancy techniques for general-purpose and specific-purpose processors, such as VLIW (Very Long Instruction Word) and CGRA (Coarse-Grained Reconfigurable Architectures).

show abstract

Section: Discussionmentioning

confidence: 99%

Survey of Software-Implemented Soft Error Protection

2022

Electronics

View full text Add to dashboard Cite

show abstract

“…Recent works that study the vulnerability in the presence of soft errors in various accelerators are reviewed in [4]. These works are based on either neutron beam experiments on real platforms [7], [11], or fault injections using either highlevel simulation [12]- [14], or emulation [15]- [19]. This paper extends our previous work in [18], [19], an emulation-based fault injection framework, to provide fine-grain vulnerability analysis of a resource constrained edge accelerator architecture.…”

Section: Introductionmentioning

confidence: 94%

Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators

Corneliou

Nikolaou

Michael

et al. 2021

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

View full text Add to dashboard Cite

The use of Neural Network (NN) inference on edge devices necessitates the development of customized Neural Inference Accelerators (NIA) in an attempt to meet performance and accuracy requirements. However, edge infrastructure often relies on highly constrained resources with limited power budget and area footprint. At the same time, reliability is very crucial, especially, for critical applications and trade-offs area and power due to the needed for protection. In this paper, we study the soft-error vulnerability of an edge NIA, using an emulationbased fault injection framework, which allows for accurate and fine-grained analysis. We consider the tinyTPU architecture, which resembles Google's Tensor Processing Unit (TPU) but is optimized for edge-based applications. Through a proposed error outcome taxonomy for NN-based algorithms, we study the criticality of each NIA component and explore their vulnerability to Single Event Upsets (SEU), while providing analysis of performance-accuracy trade-offs such as using smaller NN models and periodic memory refresh. Further, through analysis of the tinyTPU architecture, we manage to considerably reduce the emulation time for components with non-persistent faults.

show abstract

“…Kaliorakis et al [8] were the first ones to be concerned with the accuracy of such FI frameworks based on virtual platforms, comparing FI implementations for gem5 [12] and MARSS [24]. In the same sense, Chatzidimitriou et al [9] proposed to analyse the soft error rate accuracy of a gem5based FI framework against results obtained from a neutron beam experiment, considering an Arm Cortex-A9 processor and 13 benchmarks. The proposed work is complementary to [9] because it considers other parameters (e.g.…”

Section: Related Workmentioning

confidence: 99%

“…While the gain in simulation speed is trivially observed in VP simulators based on just-in-time (JIT) dynamic binary translation, the soft error assessment consistency of underlying fault injection frameworks remains unclear. An initial effort to investigate the soft error consistency of VP simulators has been conducted in [5,8,9]. Common findings of these works is that higher level FI approaches provide more flexibility and simulation performance at the cost of accuracy, mostly resulting from the lack of microarchitecture and timing modelling aspects.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Abich

Garibotti

Bandeira

et al. 2021

IET Computers & Digital Tech

View full text Add to dashboard Cite

Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high‐charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just‐in‐time fault injection simulator (OVPsim‐FIM) against fault injection campaigns conducted with event‐driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single‐core fault injection campaigns are performed on RTL descriptions of Arm Cortex‐M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex‐A9 scenarios. Campaigns consider different open‐source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim‐FIM is more than 1000× faster than cycle‐accurate simulators and up to 312× faster than event‐driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.

show abstract

Demystifying Soft Error Assessment Strategies on ARM CPUs: Microarchitectural Fault Injection vs. Neutron Beam Experiments

Cited by 43 publications

References 56 publications

Survey of Software-Implemented Soft Error Protection

Survey of Software-Implemented Soft Error Protection

Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Contact Info

Product

Resources

About