2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON) 2017
DOI: 10.1109/upcon.2017.8251108
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Design and analysis four bit hybrid full adder cell using gate diffusion input technique and domino logic

Rishab Goyal
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Shubham Sharma
2
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Hybrid 4:16 Decoder Using Variable Bias GDI Technique

Kandasamy
1
,
Sanjeevaiah
2
,
Telagam
3
et al. 2021
Lecture Notes in Electrical Engineering
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Hybrid 4:16 Decoder Using Variable Bias GDI Technique

Kandasamy
1
,
Sanjeevaiah
2
,
Telagam
3
et al. 2021
Lecture Notes in Electrical Engineering
0
0
0
0
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XNOR-XOR based Full Adder Using Double Pass Transistor Logic

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Soundaryya3
2023
2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS
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An MTCMOS Subthreshold-Leakage Reduction Algorithm

Sharroush
1
2020
2020 2nd Novel Intelligent and Leading Emerging Sciences Conference (NILES)
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