Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

Abstract

High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the BE transforms the bubble free code into binary code. A Tanner EDA with 250-nm Technology is used to implement the C-FADC. The proposed design achieves ENOB of 3.56, uses 3.24 mW of power, and has a FOM of 0.274pJ/conv.-step at an input frequency of 85 MHz. The suggested C-FADC has differential and integral nonlinearities of ±0.65 LSB and +0.45/-0.5 LSB, respectively.

A 78-MHz BW Continuous-Time Sigma-Delta ADC with Programmable VCO Quantizer

“…The analog-to-digital converter (ADC), as an interface circuit connecting physical signals and digital signals that can process information, is of great importance to promote information technology. In particular, with the rapid development of artificial intelligence [1], the Internet of Things [2], cloud computing and 6 G communication technologies [3], high-bandwidth and low-power ADC has become a research hotspot [4,5]. Sigma-delta ADC is widely recognized for its unique oversampling and noise-shaping techniques, achieving lower cost and higher performance.…”