Design and analysis of a low power consumption high speed frequency divider by 2/3

Murtaza, Cristian; Cojan, Radu Adrian

doi:10.1109/smicnd.2010.5650526

Cited by 3 publications

(1 citation statement)

References 3 publications

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“…A TSCP divider architecture shown in Fig. 5 exploits the master-slave configuration presented in [19]. The master-slave architecture prevents glitches, which would occur at the output for the traditional flipflop.…”

Section: Frequency Dividermentioning

confidence: 99%

ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

Kayed¹,

Saleh²,

Shawkey³

2022

Preprint

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This paper demonstrates an on-off keying (OOK) super-regenerative quenching transmitter operating in 402- 405MHz MICs band applications. To reduce power consumption, the transmitter is controlled by a novel digital quenching signal controller that generates a digital control signal to start transmitter operation when a baseband signal is input to the transmitter. The digital signal controller consists of an envelope detector, a comparator, and a quench timer designed using a state machine to synchronize the operation between the digital controller and the input baseband signal. The transmitter consists of a Colpitts oscillator operating in double operating frequency followed by a frequency divider by 2, this configuration reduces system area and improves phase noise and signal spectrum. The proposed transmitter is implemented using UMC 130nm CMOS technology, and a 1.2V supply. Simulation shows that the proposed transmitter can meet MICS band mask specifications with data rates up to 1Mbps and total power dissipation of 537uW.

show abstract

Section: Frequency Dividermentioning

confidence: 99%

ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

Kayed¹,

Saleh²,

Shawkey³

2022

Preprint

View full text Add to dashboard Cite

show abstract

Development of a Self-Correcting CMOS-Based Clock Generator for Wireless Sensor Network in 90nm Process Technology

Avelino¹,

Precilla²,

Lenette³

et al. 2018

TENCON 2018 - 2018 IEEE Region 10 Conference

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ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

2022

View full text Add to dashboard Cite

This paper demonstrates an on–off keying (OOK) super-regenerative quenching transmitter operating in 402–405 MHz MICs band applications. To reduce power consumption, the transmitter is controlled by a novel digital quenching signal controller that generates a digital control signal to start transmitter operation when a baseband signal is input to the transmitter. The digital signal controller consists of an envelope detector, a comparator, and a quench timer designed using a state machine to synchronize the operation between the digital controller and the input baseband signal. The transmitter consists of a Colpitts oscillator operating in double operating frequency followed by a frequency divider by 2; this configuration reduces system area and improves phase noise and signal spectrum. The proposed transmitter is implemented using UMC 130 nm CMOS technology and a 1.2 V supply. Simulation shows that the proposed transmitter can meet MICS band mask specifications with data rates up to 1 Mbps and total power dissipation of 537 uW.

show abstract

Design and analysis of a low power consumption high speed frequency divider by 2/3

Cited by 3 publications

References 3 publications

ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

Development of a Self-Correcting CMOS-Based Clock Generator for Wireless Sensor Network in 90nm Process Technology

ULP Super Regenerative Transmitter with Digital Quenching Signal Controller

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