2018 Internat2018 International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC)ional Confer 2018
DOI: 10.1109/iccpeic.2018.8525224
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Design and Analysis of Wallace Tree Multiplier for CMOS and CPL Logic

S. Nagaraj1,
K. Thyagarajan2,
D. Srihari3
et al.
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Cited by 5 publications
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Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Gudivada
1
,
Kumar
2
,
Jajula
3
et al. 2021
Materials Today: Proceedings
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Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Gudivada
1
,
Kumar
2
,
Jajula
3
et al. 2021
Materials Today: Proceedings
0
0
0
0
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A Comparative Analysis of Switched Gate Implementations in Wallace Tree Multipliers

Pallati,
Bandi,
Chandra Sekhar
et al. 2024
2024 3rd International Conference on Artificial Intelligence for Internet of Things (AIIoT)
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Design and Implementation of 8-Bit Vedic Multiplier Using Cadence 45nm Technology

Sharmila,
Saikumar,
Pranav Sai Subhash
et al. 2024
2024 Fourth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT)
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