Design and architectures for dependable embedded systems

Henkel, Jörg; Bauer, Lars; Becker, Joachim; Bringmann, Oliver; Brinkschulte, Uwe; Chakraborty, Samarjit; Engel, Michael; Ernst, Rolf; Härtig, Hermann; Hedrich, Lars; Herkersdorf, Andreas; Kapitza, Rüdiger; Lohmann, Daniel; Marwedel, Peter; Platzner, Marco; Rosenstiel, Wolfgang; Schlichtmann, Ulf; Spinczyk, Olaf; Tahoori, Mehdi B.; Teich, Jürgen; Wehn, Norbert; Wunderlich, Hans-Joachim

doi:10.1145/2039370.2039384

Cited by 81 publications

(36 citation statements)

References 39 publications

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“…Error steering toward less important (depending on the application) parts of ISA during design or at runtime can be done with ISA extensions specifying latency and reliability constraints to the hardware. Annotations indicating access patterns, reliability requirements [90], etc. of code segments as well as data can be used effectively especially in case of heterogeneous circuits and systems (e.g., [19]).…”

Section: Implications For Circuits and Architecturesmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

138

116

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Abstract-Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software. This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. The envisioned underdesigned and opportunistic computing (UnO) machines face a number of challenges related to the sensing infrastructure and software interfaces that can effectively utilize the sensory data. In this paper, we outline specific sensing mechanisms that we have developed and their potential use in building UnO machines.

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Section: Implications For Circuits and Architecturesmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

138

116

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“…The delay fault shows itself only at speed while design is working with the target clock frequency. Delay faults are mostly due to aggressive place and route [40], circuit aging, PVT variations, and transistor wear out [41], [42]. Fig.…”

Section: Delay Fault Modelmentioning

confidence: 99%

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Kakoee

Bertacco

Benini

2014

IEEE Trans. Comput.

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Abstract-In this work, we propose a distributed functional test mechanism for NoCs which scales to large-scale networks with general topologies and routing algorithms. Each router and its links are tested using neighbors in different phases. The router under test is in test mode while all other parts of the NoC are operational. We use triple module redundancy (TMR) for the robustness of all testing components that are added into the switch. Experimental results show that our functional test approach can detect stuck-at, short and delay faults in the routers and links. Our approach achieves 100 percent stuck-at fault coverage for the data path and 85 percent for the control paths including routing logic, FIFO's control path, and the arbiter of a 5 Â 5 router. We also show that our approach is able to detect delay faults in critical control and data paths. Synthesis results show that the area overhead of our test components with TMR support is 20 percent for covering stuck-at, delay, and short-wire faults and 7 percent for covering only stuck-at and delay faults in the 5 Â 5 router. Simulation results show that our online testing approach has an average latency overhead of 3 percent in PARSEC traffic benchmarks on an 8 Â 8 NoC.

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“…Variability is a growing challenge in microelectronic designs [1], [2]. Static process variations manifest themselves as die-to-die and within-die variations.…”

Section: Introductionmentioning

confidence: 99%

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

Rahimi¹,

Marongiu²,

Gupta³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floatingpoint units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an applicationdriven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

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Design and architectures for dependable embedded systems

Cited by 81 publications

References 39 publications

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

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