Design and implementation of a MAC controller for the IEEE802.11 wireless LAN

Iliopoulos, Marios; Maniatopoulos, A.; Antonakopoulos, Theodore

doi:10.1080/00207210010013210

Cited by 2 publications

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“…An external memory controller would consume approximately 4K gates while a PCMCIA Interface controller will use 7K equivalent gates [38]. Timers and Interrupt Controller for a WiFi take 8.8K equivalent gates [38].…”

Section: Drmp Estimatesmentioning

confidence: 99%

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A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

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Nabi, Syed Waqar (2009) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. EngD thesis.http://theses.gla.ac.uk/865/ Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non-commercial research or study, without prior permission or charge This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the Author When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given Copyright c Syed Waqar Nabi October 2008In the name of Allah, the Beneficent, the Merciful.Read: In the name of thy Lord Who createth, Createth man from a clot. Read: And thy Lord is the Most Bounteous, Who teacheth by the pen, Teacheth man that which he knew not. Nay, but verily man is rebellious That he thinketh himself independent! Lo! unto thy Lord is the return.The Quran; Chapter 96, Verses 1-7 i Abstract DRMP, a Dynamically Reconfigurable MAC Processor, is an innovative, dynamically reconfigurable System-on-Chip architecture. The architecture exploits substantial overlaps in the functionality of different wireless MAC layers. Its flexibility is specialized for addressing the requirements of the MAC layer of wireless standards. It is targeted at consumer, multi-standard, handheld devices, and its design is meant to address the balance of flexibility and power-efficiency that this target market demands. The DRMP reconfigures packet-by-packet on the fly, allowing execution of concurrent protocol modes on a single hardware co-processor. An interrupt-driven programming model has also been presented and shown to implement the protocol state-machine of the three protocols on a CPU. These features will allow the DRMP to replace three MAC processors in a hand-held device. The most innovative component of the DRMP architecture is its Interface and Reconfiguration Controller. It uses a combination of asynchronous controllers to dynamically reconfigure the functional units in the architecture and delegate MAC tasks to them. The architecture has been modeled in Simulink at cycle-approximate abstraction. Results of simulations involving transmission and reception of packets have been presented, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Its heterogeneous and coarse-grained functional units, limited connectivity requirements between these units, and proportionally large time that these resources are idle, promise a very modest power-consumption, suitable for mobile devices, while offering flexibility to implement different MAC protocols. The Institute of System Level Integration in general, the EngD center and Sian Williams in particular, deserve a special t...

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Section: Drmp Estimatesmentioning

confidence: 99%

“…The physical interface for a WiFi implementation in reference [38] includes: Tx and Rx state-machines, FIFOs, registers for access to an AMBA bus, Tx and Rx DMA engine, Tx and Rx CRC and shift registers. It consumes approximately 20K equivalent ASIC gates.…”

Section: Drmp Estimatesmentioning

confidence: 99%