Design and Implementation of a Reversible Logic Based 8-Bit Arithmetic and Logic Unit

Arunachalam, Kamaraj; Perumalsamy, Marichamy; Sundaram, C. Kalyana; Kumar, J. Senthil

doi:10.2316/journal.202.2014.2.202-3832

Cited by 3 publications

(1 citation statement)

References 10 publications

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“…Implementation and design for ALU is discussed with reversible logic in [12]. Multiplier and accumulate unit (MAC) is used for the multiplication of two numbers and adding this product to the accumulator.…”

Section: Introductionmentioning

confidence: 99%

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Dudhane¹

2020

IJETER

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In the new world of science and technology with the tremendous changes in electronic gadgets such as microprocessors and microcontrollers, becoming an important blocks of the electronics industry. For any processor, CPU has integral part which is ALU, responsible for the efficient work of the processor. This paper integrates the computing ability of 8 bit processor with 16 bit cooperative arithmetic and logic unit and 8by8 bit multiplication. In this technology, 8 bit processor keeps its ability with excellent input/ output control with maintaining its simple architecture and low power consumption. FPGA offers a platform for designing and implementing soft cores for improvement in execution time and developing IP cores. 16F84 RISC processor is designed module wise developed with HDL language and implemented using FPGA with enhanced architecture. The results are obtained in three ways as firstly designing and implementing 16 bit CALU with 8 bit processor, secondly 8by8 bit multiplier and thirdly combined integration of 16 bit CALU and 8by8 bit multiplier. Simulation result for 8 bit multiplier shows execution time of 109.241 ns, with 16 bit CALU is 674.66 ns and with multiplier and 16 bit CALU is 583.33 ns, 76.09 % cycle saving is achieved with the implementation using reconfigurable hardware, improving execution time from 674.66 ns to 583.33 ns. The design is configured on Xilinx 14.6 using FPGA and implemented using Verilog or HDL.

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Section: Introductionmentioning

confidence: 99%

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Dudhane¹

2020

IJETER

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Design and Implementation of 8 Bit Shift Register using Reversible Logic

Rajeshwari

Hongal

Shettar

2018

2018 International Conference on Current Trends Towards Converging Technologies (ICCTCT)

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Fault Tolerant ALU using Parity Preserving Reversible Logic Gates

Thakral

Bansal

2016

IJMECS

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Abstract-Demand of reliable computing has been a major concern since the dawn of the electronic digital computer age. Reliable computing has various applications not only in the field of military, aerospace and communication but even contemporary commercial applications to fulfill today's automated life style. The tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI) is facing power dissipation as one of the main barriers. To overcome this barrier, researchers need to enter into the reversible logic domain. Making a reversible circuit robust or fault tolerant is much more difficult than a conventional logic circuit. Fault tolerance can be achieved in a system by using parity bits. The main aim of this paper is to come up with a new fault tolerant ALU design based on parity preserving reversible logic gates with improved quantum cost and power overhead as compare to existing fault tolerance based ALU designs. The most stringent requirement for fault tolerant ALU is in real time control system where faulty computation jeopardizes human life or other catastrophic effects.Implentation of proposed design is done using Xilinx ISE design suit 14.2 tool and its performance over existing ALU designs is qualitatively analyzed.

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Design and Implementation of a Reversible Logic Based 8-Bit Arithmetic and Logic Unit

Cited by 3 publications

References 10 publications

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Architectural Enhancement of Processor with 8 Bit Multiplier and 16 Bit Co-operative ALU using VHDL

Design and Implementation of 8 Bit Shift Register using Reversible Logic

Fault Tolerant ALU using Parity Preserving Reversible Logic Gates

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