Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios

Grand, Michael; Bossuet, Lilian; Gal, Bertrand Le; Gogniat, Guy; Dallet, Dominique

doi:10.1007/978-3-642-19475-7_5

Cited by 8 publications

(11 citation statements)

References 8 publications

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“…Mixed with hardware reconfiguration properties, parallelism can ensure flexibility and high performance in cryptographic processing. Some recent applications, such as software radio, which manages many communication channels using a variety of cryptographic services, highlight such flexible and powerful architecture [Grand et al 2011]. There is also a need for heterogeneous MPSoC (multi-processor system-on-a-chip) that can embed many crypto engines.…”

Section: Secure By Designmentioning

confidence: 99%

“…The designer can take advantage of the flexibility of this solution by using an appropriate hardware-software codesign tool when defining the boundary between hardwired and soft functions. Very recent work on high-performance (high-throughput) systems demonstrated the interest of continuing development in this area, while at the same time extending it towards multi-crypto-processor architectures [Grand et al 2011]. The way is open to new concepts such as crypto array and MCryptoPSoC (Multi-CryptoProcessor System-on-a-Chip).…”

Section: Throughput/flexibility/security Tradeoffmentioning

confidence: 99%

“…9. Four-core MCCP architecture [Grand et al 2011]. the radio (that processes plaintext data) and the black part of the radio (that processes encrypted data and sends/receives data to/from the RF component).…”

Section: Multicore Crypto Processormentioning

confidence: 99%

“…One example of a multicore crypto processor, the MCCP [Grand et al 2011], focuses on designing a crypto processor, which has to provide the cryptographic services (e.g., secure SCA [Martin et al 2008]) required by a secure SDR (Software-Defined Radio) base station. For this purpose, the crypto processor is embedded in a much larger component [Grand et al 2009], which is placed at the boundary between the red part of 41:18 L. Bossuet et al Fig.…”

Section: Multicore Crypto Processormentioning

confidence: 99%

“…The MCCP [Grand et al 2011] was designed considering that an SDR base station has to process several channels at the same time. The architecture proposed embeds several cryptographic cores to enable flexible and efficient enciphering/deciphering of the channel.…”

Section: Multicore Crypto Processormentioning

confidence: 99%

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Architectures of flexible symmetric key crypto engines—a survey

et al. 2013

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Throughput, flexibility, and security form the design trilogy of reconfigurable crypto engines; they must be carefully considered without reducing the major role of classical design constraints, such as surface, power consumption, dependability, and cost. Applications such as network security, Virtual Private Networks (VPN), Digital Rights Management (DRM), and pay per view have drawn attention to these three constraints. For more than ten years, many studies in the field of cryptographic engineering have focused on the design of optimized high-throughput hardware cryptographic cores (e.g., symmetric and asymmetric key block ciphers, stream ciphers, and hash functions). The flexibility of cryptographic systems plays a very important role in their practical application. Reconfigurable hardware systems can evolve with algorithms, face up to new types of attacks, and guarantee interoperability between countries and institutions. The flexibility of reconfigurable crypto processors and crypto coprocessors has reached new levels with the emergence of dynamically reconfigurable hardware architectures and tools. Last but not least, the security of systems that handle confidential information needs to be thoroughly evaluated at the design stage in order to meet security objectives that depend on the importance of the information to be protected and on the cost of protection. Usually, designers tackle security problems at the same time as other design constraints and in many cases target only one security objective, for example, a side-channel attack countermeasures, fault tolerance capability, or the monitoring of the device environment. Only a few authors have addressed all three design constraints at the same time. In particular, key management security (e.g., secure key generation and transmission, the use of a hierarchical key structure composed of session keys and master keys) has frequently been neglected to the benefit of performance and/or flexibility. Nevertheless, a few authors propose original processor architectures based on multi-crypto-processor structures and reconfigurable cryptographic arrays. In this article, we review published works on symmetric key crypto engines and present current trends and design challenges.

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Section: Secure By Designmentioning

confidence: 99%

Section: Throughput/flexibility/security Tradeoffmentioning

confidence: 99%

Section: Multicore Crypto Processormentioning

confidence: 99%

Section: Multicore Crypto Processormentioning

confidence: 99%

Section: Multicore Crypto Processormentioning

confidence: 99%

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Architectures of flexible symmetric key crypto engines—a survey

et al. 2013

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Blockchain based secret key management for trusted platform module standard in reconfigurable platform

Paul,

Ghosh,

Panigrahi

et al. 2024

Concurrency and Computation

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SummaryThe growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data, make it more important to keep secret keys safe and secure. A few major issues of secret keys, like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and nondestruction of keys can compromise the whole security system severely. In this work, we propose a field programmable gate array (FPGA)‐based trusted platform module (TPM) framework for operating system companies and OS users, utilizing blockchain to address NIST‐recommended secret key management issues. The security processor used in OS user machines is partitioned into three areas such that processor area, confidential area, and crypto area. The isolated secret key memory in confidential area, along with a private blockchain (BC) can log the life cycle of secret keys of TPM standard. We have also implemented a special custom bus interconnect, which receives custom crypto instructions from Processing Element (PE). During the execution of crypto instructions, the architecture ensures that secret keys are present in confidential area and crypto area but never in the processor area. The movements of secret keys between confidential area, and crypto area are recorded cryptographically after the proper authentication process controlled by the proposed hardware‐based private BC framework. To the best of our knowledge, this work is the first attempt to implement a blockchain‐based framework between OS company and OS users to address NIST recommended secret key management issues of TPM standard hardware environment. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is nominal. The proposed architecture is implemented with Xilinx EDA tool using FPGA board.

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