Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing

Abstract

This paper proposes a flexible dual-mode soft-output multiple-input multiple-output (MIMO) detector to support open-loop and closed-loop in Chinese enhanced ultra high throughput (EUHT) wireless local area network (LAN) standard. The proposed detector uses minimum mean square error (MMSE) sorted QR decomposition (MMSE-SQRD) to produce channel preprocessing result, which is realized by a modified systolic array architecture with concurrent sorting. Moreover, the adopted square-root MMSE algorithm for closed-loop reuses MMSE-SQRD preprocessing to largely save hardware overhead. In addition, an optimized K-Best detection algorithm is proposed for open-loop, which increases throughput by odd-even parallel sorting and produces high quality soft-output with discarded paths (DPs). A flexible VLSI architecture is designed for the proposed dual-mode detector, which supports antennas and BPSK 64-QAM modulation configuration. Implemented in SMIC 65 nm CMOS technology, the detector is capable of running at 550 MHz, which has a maximum throughput of 2.64 Gb/s for K-Best detection and 3.3 Gb/s for linear MMSE detection. The proposed detector is competitive to recent published works and meets the data-rate requirement of the EUHT standard.Index Terms-Channel preprocessing, K-Best detection, minimum mean square error (MMSE) detection, multiple-input multiple-output (MIMO), sorted QR decomposition (SQRD).

Programmable ASIPs for Multimode MIMO Transceiver

“…The ten cores take a total area of 2.93 mm 2 which is comparable to the 2.1 mm 2 of [11]. Similarly, 55 cores working on the same number of OFDM subcarriers can reach the scaled throughput of the ASIC presented in [14]. The total multiprocessor area is 16.11 mm 2 that is comparable to the 12.53 mm 2 of [14].…”

“…We argue that such designs are best suited for an ASIC. Yan et al presented a dual-mode architecture that supports MMSE and K-best LSD in [14]. The architecture is non-programmable and takes a large area.…”

“…Our design provides a better compromise between flexibility and hardware efficiency. It should be noted that [11] and [14] also includes the preprocessing circuitry, so the comparison in Table II is not entirely fair. Instead of traditional ASIPs, a no instruction based computer (NISC) based approach was introduced in [27] for an iterative MIMO equalizer and demapper.…”

“…The group of control signals are packed in the [27] achieves significantly higher scaled throughput than the multimode implementations. The architectures that support several algorithms ( [11], [14] and proposed) achieves lower scaled throughput because the whole design cannot be optimized for a single algorithm. A homogeneous multiprocessor system consisting of several TTA processor proposed in this paper can increase the throughput.…”

“…A plethora of application specific integrated circuit (ASIC) and ASIP implementations supporting a single MIMO detection algorithm can be found in the literature [6]- [10]. A few digital very large scale integration (VLSI) implementations for multimode MIMO detection can also be found in [11]- [14] We present a MIMO detector ASIP that supports minimum mean-square error (MMSE), 8-best list sphere detection (LSD) and two variants of selective spanning for fast enumeration (SSFE) detection algorithms. The ASIP delivers 6.16 -66.66 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology.…”