2017 International Conference on Communication and Signal Processing (ICCSP) 2017

DOI: 10.1109/iccsp.2017.8286401

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Design and implementation of low power test pattern generator using low transitions LFSR

Tejas Thubrikar

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Shweta Gaidhani

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et al.

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Cited by 10 publications

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Analysis of Coupling Transition for the Encoded Data and Its Logical Level Power Analysis

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2021

Data Engineering and Communication Technology

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Analysis of Coupling Transition for the Encoded Data and Its Logical Level Power Analysis

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2021

Data Engineering and Communication Technology

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Low Powered Self-Testable ALU

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2021

IOP Conf. Ser.: Mater. Sci. Eng.

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The Arithmetic and Logic Unit(ALU) is a Significant Segment of a CPU as it does all the arithmetic and logical operations and computations required by all the processes running inside the CPU. Being such an important part inside the processor, It requires more power and thus it would be efficient and feasible if it can run on low power and also can test for any faults in the circuit itself. This paper completely focuses on building a Low Powered ALU with the implementation of Built-In Self-Test(BIST) mechanism for efficient arithmetic and logical operations. In the design, power-efficient circuits such as Wallace Tree Multiplier and Carry Look-Ahead Adder is being used. The created design is synthesized and simulated on the Xilinx Vivado software tool and implemented on Digilent Xilinx Basys 3 Artix-7 (XC7A35T-1CPG236C) Field Programmable Gate Array (FPGA). The overall power consumption of the design is 75mW and the ALU has self-testability function.

FPGA Implementation of Efficient and Low Power Test Pattern Generator

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2022

2022 2nd Asian Conference on Innovation in Technology (ASIANCON)

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