Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier

High-speed binary coded decimal digit multipliers with multiple error detection

“…So far, many designs and methods have been proposed to enhance the BCD or decimal multipliers with respect to area, power or delay. Many of the previous designs and methods are based on different BCD-based coding techniques [7][8][9] or utilizing optimal adder structures for partial product generation and reduction [10][11][12][13][14][15] to reduce area, delay or power consumption. Some designs utilize the methods for improving the implementation of BCD multipliers on FPGAs [16][17][18].…”