Design and Verification for PCI Express Controller

Abstract

In this paper, we design a PCI Express controller for Endpoint. The controller supports full functionality of Transaction Layer and Data Link Layer of PCI Express. We also propose an efficient buffer management scheme to obey replay mechanism. We employ 80C51 to effectively manage designed functional blocks and implement Real-Time OS, MicroC/OS II on 80C51. We also code software under real time environment. This coded software fully covers the PCI Express protocols; supporting the replay mechanism, checking and generating error message, processing TLP acknowledgment, and management for exchanging Flow Control. For verification, we build a test bench including functional models of Host Bridge, Local Master, Local Slave, and Protocol Monitor. We also define the instructions to easily generate situations that it will occur in actual operation. We propose an effective verification to compliance and corner case testing using Reference Model, Random Generator, and Compare Engine. This verification environment is excellent to find error which it not detected by general test vector.

Accelerating functional verification of PCI express endpoint by emulating host system using PCI express core

“…In [6], Hyun and Seong have written test bench for verifying PCIe Endpoint functionality; the testbench includes functional models of Host Bridge, local masters, local slaves and protocol monitor.…”

Sampling and Reconstruction of Ordered Sets in PCIe 3.0

“…More recent revisions of the PCIe standard provide hardware support for I/O virtualization [1], [2], [3], [4]. [5] describes the controller support functionality of Transaction Layer and Data Link Layer of PCIe which also propose an efficient buffer management scheme to obey replay mechanism.…”