Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range

Abstract

In this paper, we present the design considerations for a sub-25μW phase-locked loop (PLL) with a wide tuning range and multi-phase outputs, which makes it suitable for applications that involve clock-and-data-recovery with variable data rates, such as broadband body-area-networks. Several architectures for the voltagecontrolled-oscillator (VCO) are analyzed for power and performance, and the considerations for keeping the VCO's low-dropout-regulator (LDO) within the loop and outside the loop are discussed. Power consumption is minimized by keeping the LDO outside the loop, which exempts the error-amplifier (EA) from the bandwidth constraints posed by the PLL. Conforming to the analysis, the PLL is designed and simulated in a standard 65nm CMOS process, and the results show that energy-efficiencies as low as 70fJ/cycle can be achieved with a tuning range of 1-450MHz along with multi-phase outputs with RMS timing jitter of 11.4ps (frequency offset < 100ppm) from a 31-stage split-tuned ring oscillator VCO.