Design for Soft Error Resiliency in Internet Core Routers

Silburt, A.L.; Evans, Adrian; Perryman, Ian; Wen, Shi-Jie; Alexandrescu, Dan

doi:10.1109/tns.2009.2033915

Cited by 24 publications

(4 citation statements)

References 7 publications

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“…That is, the hardened flip-flops may be used to replace all the flip-flops in the design or to selectively harden only the critical blocks. Previous works have shown that a significant fraction of all flip-flop upsets gets masked due to logic and timing derating effects [14,15]. Furthermore, most of the upsets that reach the output were shown to originate from a few functional blocks in a network processor as shown in Fig.…”

Section: Design Hardening Comparisonmentioning

confidence: 96%

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

Narasimham

Chandrasekharan

Wang

et al. 2014

2014 IEEE International Reliability Physics Symposium

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A novel pulsed-latch design using hysteresis that operates similarly to an edge-triggered flip-flop with improved SER performance is presented. Design was implemented along with standard D-flip-flop (D-FF) and DICE flip-flop in a 20 nm CMOS process. Alpha and Neutron SER test results indicate ~26× and ~3× better SER hardness respectively for the pulsedhysteresis-latch compared to D-FF. The design also benefits from a 25% higher speed and has a low area overhead of ~8% over the D-FF. A typical processor utilizing the pulsed-hysteresis-latch design can benefit from a ~5× overall SER reduction which is shown to be better than targeted DICE-FF based hardening, both in terms of SER reduction and performance penalty.

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Section: Design Hardening Comparisonmentioning

confidence: 96%

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

Narasimham

Chandrasekharan

Wang

et al. 2014

2014 IEEE International Reliability Physics Symposium

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“…Table 4 provides examples of typical failure modes at different levels in a system. At the system level, the rates of high-level events (such as packet-drops, short outages and undetected failures) are important [5]. At the chip or blocklevel, typical failure modes would be the occurrence of parity errors, uncorrectable ECC errors, or packet drops.…”

Section: Improved Reliability Modeling Strategiesmentioning

confidence: 99%

System-level reliability using component-level failure signatures

Wong

Bhuva

Evans

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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International audienceSystem-level Mean Time Between Failures (MTBF) is usually evaluated using individual component-level reliability metrics. System-level failures are categorized by Reliability, Availability and Serviceability (RAS) metrics. However, RAS evaluation at the system-level requires precise mapping between component failure modes, their system failure signatures and system reliability requirements. In this paper, RAS analysis carried out on internet switches in a top-down hierarchical fashion is presented. Results show availability of failure classification at a lower-level of design allows for better fault management and improved RAS metrics at the system-level. A hierarchical modeling format is proposed to standardize the reporting of component failure modes to improve the system level modeling of RAS

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“…(4) More direct quantification by chip/board level irradiation tests are also pursued [36][37][38][39]. This method is quite straight forward, but time and cost consuming cannot be avoided.…”

Section: Revisions Needed For Jesd89amentioning

confidence: 99%

Novel SER standards: Backgrounds and methodologies

Ibe

Shimbo

Toba

et al. 2010

2010 IEEE International Conference on Integrated Circuit Design and Technology

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Standard methods to quantify SER susceptibility in memory devices have been established during 2000-2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.

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Design for Soft Error Resiliency in Internet Core Routers

Cited by 24 publications

References 7 publications

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

System-level reliability using component-level failure signatures

Novel SER standards: Backgrounds and methodologies

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