Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip

Molyneaux, R.; Ziaja, T.; Kim, Hong; Aryani, S.; Hwang, Sungbae; Hsieh, Ang-Chih

doi:10.1109/test.2007.4437561

Cited by 21 publications

(5 citation statements)

References 1 publication

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“…It is clear that scan partition can help reduce the test time, test data volume and test power [11,12]. However, partitioning method usually leads to a large area overhead by adding wrapper cells, and the area overhead will be increased linearly with the partition number.…”

Section: B Scan Partitionmentioning

confidence: 99%

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Qi¹,

Liu²,

Li³

et al. 2009

2009 Asian Test Symposium

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This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (Test Access Mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a Data-Synchronous-Comparator (DSC) is proposed for comparing the scan responses of the identical cores.

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Section: B Scan Partitionmentioning

confidence: 99%

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Qi¹,

Liu²,

Li³

et al. 2009

2009 Asian Test Symposium

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“…On the other side, multicore processor like the Cell processor [14] , the Niagra2 processor [15] , and the UltraSPARC CMT processor [16] use the dedicated scan inputs and outputs for each core. This approach enables the diagnosis and determination of defective cores easier but leads to more test time since the length of scan chains is much longer.…”

Section: Introductionmentioning

confidence: 99%

Design for Testability Features of Godson-3 Multicore Microprocessor

Liu

et al. 2011

J. Comput. Sci. Technol.

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This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

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“…Among these approaches, few of them take full advantage of the fact that the multiple cores under test are identical. In the test schemes of [10]- [11], each core has dedicated scan inputs/outputs and the scan chains of each core are made independent to facilitate the identification of faulty cores. However, this test scheme consumes higher test time since the length of each scan chain is longer.…”

Section: Introductionmentioning

confidence: 99%

A low-cost and scalable test architecture for multi-core chips

Chi

2010

2010 15th IEEE European Test Symposium

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Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a twodimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core.

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Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip

Cited by 21 publications

References 1 publication

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Design for Testability Features of Godson-3 Multicore Microprocessor

A low-cost and scalable test architecture for multi-core chips

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