Design for testability for path delay faults in sequential circuits

Abstract

Abstruct-We experimentally study the reasons for low coverage of path delay faults in several sequential benchmark circuits. Causes for undetected faults are classified htto three categories: (A) Combinationally nonactivated paths, (B) Sequentially nonactivated paths, and (C) Unobservable fault effect. The type A faults can only be made detectable by modtfyhtg or resynthesizing the combinational logic as has been discussed by others. We fhtd that almost 80% of sequentially untested faults are in category B. Most are not activated because the two successive states necessary to create a transition and to propagate it through the path cannot be produced in the sequential circuit.We study the partial scan technique in which flipflops are scanned to break cycles and show that a substantial increase in the coverage of path delay faults is p~ible.

A method of test generation for path delay faults in balanced sequential circuits

“…In order to avoid the former disadvantage, a technique for selecting paths which are targets of testing [3] and techniques for re-synthesizing circuits such that the path count is reduced [4,5] are proposed. The latter disadvantage can be avoided by synthesis-fortestability (SFT) techniques [1,6] and design-for-testability (DFT) techniques [1,7,8].…”

“…Chakraborty et al [8] classified undetected faults into three categories: (A) combinationally non-activated paths, (B) sequentially non-activated paths, and (C) unobservable fault effect. Path delay faults of the category (A) can only be made detectable by SFT or DFT and combinational logic can be designed for path delay testability [6].…”

“…Regarding the category (B), the fault effect propagation problem is almost the same as fault effect propagation problem of stuck-at fault model. Chakraborty et al [8] showed that almost of sequentially undetectable faults are in the category (B). In order to ease complexity of test generation, sequentially undetectable faults must be decreased.…”

“…In order to ease complexity of test generation, sequentially undetectable faults must be decreased. The fully enhanced scan technique [7] and the partially enhanced scan technique [8] are proposed to achieve this claim.…”

“…This disadvantage can be avoided using partial scan techniques. In the partially enhanced scan technique [8], for a sequential circuit, scan FFs are selected such that the feedback paths in the circuit are broken if these scan FFs are removed. For a sequential circuit designed by this partial scan technique, we can consider the circuit to be a feedback free circuit during test generation and test generation of the feedback free circuit is much easier than the original one.…”