Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage

Tanakamaru, Shuhei; Yamazawa, Hiroki; Tokutomi, Tsukasa; Ning, Sheyang; Takeuchi, Ken

doi:10.1109/tcsi.2014.2370171

Cited by 5 publications

(4 citation statements)

References 19 publications

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“…For PL-SPCM and SPCM, depending on the cache-line address (cache-line address modulo 3), the read response time is 15ns, 30ns, or 45ns; the read latency per strobe is about 10-15 ns [38]. Note that the TLC RRAM read latency numbers used in this paper are consistent with the MLC/TLC-STTRAM read latency trends [39,40].…”

Section: Latencysupporting

confidence: 64%

Rapid

Palangappa

Mohanram

2018

Proceedings of the International Conference on Computer-Aided Design

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RAPID is a low-overhead critical-word-first read acceleration architecture for improved performance and endurance in MLC/TLC non-volatile memories (NVMs). RAPID encodes the critical words in a cache line using only the most significant bits (MSbs) of the MLC/TLC NVM cells. Since the MSbs of an NVM cell can be decoded using a single read strobe, the data (i.e., critical words) encoded using the MSbs can be decoded with low latency. Systemlevel SPEC CPU2006 workload evaluations of a TLC RRAM architecture show that RAPID improves read latency by 21%, energy by 24%, and endurance by 2-4× over state-of-the-art striped NVM.

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Section: Latencysupporting

confidence: 64%

Rapid

Palangappa

Mohanram

2018

Proceedings of the International Conference on Computer-Aided Design

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“…For example, the BER of 3rd page is over 1.8Â higher than that of 2nd page in 2Ânm TLC [22]. Therefore, when BER 2nd_page is applied to all pages, the BER of 3rd page is underestimated about 54%.…”

Section: Total Ber Estimation and Short Retention Time Unit (Unit2)mentioning

confidence: 97%

“…9. TLC NAND has eight possible V TH states, and each state has a different SER [22]. This value also depends on the write/erase (W/E) cycle and data-retention time.…”

Section: State-error Rate (Ser) and Cell-error Rate (Cer) Estimationmentioning

confidence: 99%

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2015

Solid-State Electronics

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a b s t r a c tTo improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012(Tanakamaru et al., , 2013, which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2Ânm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4Â and 9.5Â at room-temperature (RT) and 85°C, respectively. Similarly, the acceptable BER is increased by 1.8Â and 2.3Â, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

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“…The memory cell masking scheme is not suitable for NRAM because all of the program errors are temporary errors [2]. On the other hand, RCRF recovers both broken cell errors and temporary program errors.…”

Section: A Comparison Of Rcrf and Cell Maskingmentioning

confidence: 99%

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

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A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10 8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm Al x O y resistive RAM (ReRAM) test chip.Index Terms-Carbon nanotube, emerging memory, error correcting code, memory controller, non-volatile memory, NRAM, reliability, solid-state drive, storage class memory.

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Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage

Cited by 5 publications

References 19 publications

Rapid

Rapid

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

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