2013 IEEE Photonics Conference 2013
DOI: 10.1109/ipcon.2013.6656429
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Design, modeling and fabrication of a CMOS compatible p-n junction avalanche photodiode

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Cited by 6 publications
(4 citation statements)
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“…where E is the electric field and the A, B, and m are material-dependent parameters listed in [12], [13]. The electric field and the depletion width considered in the DSMT model are calculated by solving Poissons equation and standard formula [9].…”
Section: Simulation and Measurement Resultsmentioning
confidence: 99%
“…where E is the electric field and the A, B, and m are material-dependent parameters listed in [12], [13]. The electric field and the depletion width considered in the DSMT model are calculated by solving Poissons equation and standard formula [9].…”
Section: Simulation and Measurement Resultsmentioning
confidence: 99%
“…The k value was calculated to be approximately 0.4. Note that the value of k for silicon is much larger at very high electric fields present in very thin multiplication regions (e.g., <400 nm [22] [27] than that for bulk silicon) as shown in Fig. 1 in [28].…”
Section: Section IV Experimental Validation Of the Theorymentioning
confidence: 91%
“…In order to obtain an exact analytical formula for F(x), we solve the recursive integral equations from the DSMT model [10] with zero dead space to obtain the second moments of electrons and holes, z2(x) and y2(x), respectively, under mixed injection. The recursive integral equations for the second moments of Z(x) and Y(x) are equations (22) and (23) in [10], and they are expressed below: The exponent r turns out to satisfy the same characteristic equation as in (9). Upon substituting the proposed forms from (19a) and (19b) into (18a) and (18b) and applying boundary conditions 2 ( ) = 2 (0) = 1, we obtain a system of twelve linear equations with ten unknown coefficients p1, p2, p3, p4, p5, q1, q2, q3, q4, and q5.…”
Section: B Formula For Mixed-injection Excess-noise Factormentioning
confidence: 99%
“…While = 0.02 for silicon APDs with wide junctions and low electric field, for high-speed CMOS compatible silicon APDs [15]- [16][17] [18], k approaches 1 as we reach submicrometer thicknesses [19]. When compared with the case of ≈ 0, and for a given thickness of avalanche region, this leads to an increase in the buildup time (defined as the time required for all the impact ionizations to complete, due to additional chain of ionizations from the presence of holes) as well as the tunneling current.…”
Section: Section I Introductionmentioning
confidence: 99%