Design of Efficient, Dependable SoCs Based on a Cross-Layer-Reliability Approach with Emphasis on Wireless Communication as Application and DRAM Memories

Abstract

Many applications show an inherent error resilience due to their probabilistic behavior. This inherent error resilience can be exploited to reduce the design margin for advanced technology nodes resulting in more energy and area efficient implementation. We present in this chapter a cross-layer approach for efficient reliability management in wireless baseband processing with special emphasis on memories since memories are most susceptible to dependability problems. A multiple-antenna (MIMO) system will be used as design example. Further on we focus on DRAMs (Dynamic Random Access Memories). All today’s computing systems rely on dependable DRAMs. In the future DRAM memories will become more undependable due to further scaling. This has to be counterbalanced with higher refresh rates, which leads to a higher DRAM power consumption. Recent research activities resulted in the concept of “approximate DRAM” to save power and improve performance by lowering the refresh rate or disabling refresh completely. Here, we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error-resilient applications.