Design of Efficient Reversible Multiplier

Rangaraju, H G; Suresh, Aakash Babu; Muralidhara, K. N.

doi:10.1007/978-3-642-31600-5_56

Cited by 12 publications

(8 citation statements)

References 9 publications

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“…There are several multiplier designs proposed by many authors in view of optimizing different performance parameters namely quantum cost, ancilla inputs, garbage outputs, logic depth, and a combination of these parameters. The multipliers proposed in [30,31,32,33,34] follow two phases in computing product terms. In the first phase, the partial products are computed.…”

Section: Fredkin Gate (Frg)mentioning

confidence: 99%

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

et al. 2016

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Abstract-A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing (DSP) applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60% to 90% in ancilla qubits count over the existing work on reversible quantum integer multipliers.

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Section: Fredkin Gate (Frg)mentioning

confidence: 99%

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

et al. 2016

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“…Measuring the reversible logic design in terms of number of gates is one of the major factors. In [5], the design requires a total of 40 reversible gates, [9] requires 42, total number of gates required is 44 in [7] and in [8] the number of gates required is 32 gates. The proposed Baugh-Wooley multiplier design requires 20 gates.…”

Section: Gate Count and Hardware Complexitymentioning

confidence: 99%

“…The PFAG gate is used in the multi operand addition. In [8], the authors have proposed a new reversible gate called as RAM gate. This gate is mainly used as a copying gate as fan-out is not allowed in reversible logic design.…”

Section: Introductionmentioning

confidence: 99%

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

Rajmohan¹,

Maheswari²

2016

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In today's digital era, developing digital circuits is bounded by the research towards investigating various nano devices. This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. In this work, a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh-Wooley multiplier. The proposed single multiplier cell is able to perform addition of a 1 × 1 product with the sum and carry from the previous cell. This reversible multiplier cell is useful in building up regularity in the array multipliers. The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.

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“…For example, 8!=40,320 numbers of 3-input reversible gates are possible [9]. Various circuits for reversible adder [3], [7], comparator [10], multiplexer [11], multiplier [12], [13], [14], flip-flops [8], [11], [15], counters [8], [15], registers [11], encoders [16], [17], decoders [8,[17][18][19][20][21][22][23][24][25], etc. are proposed in literatures.…”

Section: Introductionmentioning

confidence: 99%

Design of Reversible Decoder with minimum Garbage Output

Kalita¹

2020

IJATCSE

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Reversible logic is helpful in designing low power applications. Many reversible gates have been introduced in recent time for use in reversible computing. Those gates are used in the design of various circuits. In some works, decoders using reversible logic have been also proposed. This paper proposes three new reversible gates that can perform multiple logical operations alone. Using these gates, new circuits for 2-to-4 and 3-to-8 decoders are proposed followed by two new designs for general decoder. The performances of the proposed decoder circuits are studied in terms of hardware complexity, power, gate count, number of ancilla inputs and garbage outputs. Comparisons of these circuits with similar existing decoder circuits are also presented. The proposed circuits are found to have better performance characteristics particularly garbage output is least amongst available designs.

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Design of Efficient Reversible Multiplier

Cited by 12 publications

References 9 publications

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

Design of Reversible Decoder with minimum Garbage Output

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