Design of Efficiently Encodable Moderate-Length High-Rate Irregular LDPC Codes

Yang, Ming; Ryan, W.E.; Yan, Li

doi:10.1109/tcomm.2004.826367

Cited by 253 publications

(165 citation statements)

References 14 publications

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“…For this protograph, the sub-graph comprising nodes s 0 , p 0 and p 1 represents the protograph of an irregular repeat-accumulate (IRA) code [13], [26]. The remaining check node is connected to node p 2 , which is in effect precoded by an accumulator [15].…”

Section: ) G-ldpc Code Family C Imentioning

confidence: 99%

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Quasi-Cyclic Generalized LDPC Codes With Low Error Floors

Liva¹,

Ryan²,

Chiani³

2007

IEEE Trans. Commun.

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Abstract-In this paper, a novel methodology for designing structured generalized LDPC (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call LDPC code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.

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Section: ) G-ldpc Code Family C Imentioning

confidence: 99%

“…While recent advances in the design of LDPC codes have led to codes with particularly low error floors [13]- [15], the requirement of low-rate codes in some applications poses several challenges to the channel coding community. G-LDPC codes take advantage of strong component codes to achieve very low error floors.…”

Section: Introductionmentioning

confidence: 99%

Quasi-Cyclic Generalized LDPC Codes With Low Error Floors

Liva¹,

Ryan²,

Chiani³

2007

IEEE Trans. Commun.

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“…Let c = [m p] be a codeword block, where m and p indicate the information bit sequence and the parity bit sequence, respectively. From the property that the correct codeword satisfies the parity check equation, the parity bit sequence p can be derived as follows [18],…”

Section: Linear Encoding Processmentioning

confidence: 99%

7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes

Jung

Chung

Jung

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper proposes a high-throughput encoding process and encoder architecture for quasicyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

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“…Extended Irregular Repeat Accumulate (eIRA) codes [35][36][37][38][39] are a special subclass of LDPC codes that improve the systematic encoding process and generate good irregular LDPC codes for high code rate applications. The eIRA parity-check matrix can be represented by…”

Section: Qpsk Modulation Interleavingmentioning

confidence: 99%