Design of Encoder and Decoder for Q-Ary LDPC Codes Based on FPGA

Abstract

The scheme of FPGA hardware implementation based on the RA structure of encoder for q-ary LDPC codes as well as the Max-log-BP decoding are designed emphasisly. Form the performance, speed, and resource consumption situation of coder and decoder, this scheme based on FPGA can meet the requirements of the most of communication systems.