Design of high-speed RCA based 2-D bypassing multiplier for fir filter

Krishnan, Thiruvenkadam; Saravanan, S.; Pillai, Anjali S.; Anguraj, Parthibaraj

doi:10.1016/j.matpr.2020.05.803

Cited by 8 publications

(1 citation statement)

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“…Though filter 2 achieved delay improvement, cost of area and power increased because delay efficient multiplier was suitable only for time consuming path. Thiruvenkadam Krishnan et al [12] designed a high-speed area efficient RCA based 2-D bypassing multiplier for FIR implementation. It eliminated the carry multiplexer in all logic cells which was used in bypassing technique and worked based on divide and conquer principle to shorten the delay time.…”

Section: Literature Review Pramod Patali and Shahana Thottathikkulammentioning

confidence: 99%

Array Multiplier and CIA based FIR Filter for DSP applications

B.N¹,

H.G²

2021

IRJASH

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In Field Programmable Gate Array (FPGA) platform, Finite Impulse Response (FIR) filter is one of the important applications in the context of Digital Signal Processing (DSP). The traditional FIR is designed using a number of the adders, multipliers which enlarge the area of the filter architecture. Generally, the multiplier and adder are required to design the FIR filter. In this research, Array Multiplier (AM) is used in the Processing Element (PE) for multiply the filter inputs with coefficients. This research employs the Carry Increment Adder (CIA) in the accumulator for the adding output of the PE. The proposed method is named as AM-CIA-FIR filter. Due to the usage of AM and CIA adder, the hardware utilization of the proposed work is improved. The AM-CIA-FIR filter is implemented in Xilinx ISE software by using Verilog code on different Virtex devices in terms of Virtex-4, Virtex-5, and Virtex-6. This experiment results showed that AM-CIA-FIR filter has reduced 14.01 % of the FPGA utilization compared to the PSA-FIR filter design.

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Section: Literature Review Pramod Patali and Shahana Thottathikkulammentioning

confidence: 99%