Design of Lookup Table using Quaternary Logic in Voltage Mode Standard CMOS Circuit

Abstract

Designer face challenges in interconnection due to the large number of components. Interconnection and power consumption perform significant part in this paper. The shortcomings of the previous work done is high interconnections, which leads to high power usage along with more area required. The Binary logic circuits is constrained by using the number of interconnections, which increases the delay and power consumption with the boom in logic. So we design new techniques that is going to reduce the interconnection of the circuit as well as the power consumptions. Multiple-valued logic can decrease the number of required interconnections. In this paper we use quaternary to binary decoder to reduce the multiplexer control lines is the vital parts of the processing component and therefore it has a focal point of research. Therefore, the design of adders through multiplexer using multi valued logic can show to be very beneficial. So we introduce and full adder based totally at the designed quaternary lookup table.