Design of Practical Parity Generator and Parity Checker Circuits in QCA

Kumar, Dharmendra; Kumar, Chintoo; Gautam, Shipra; Mitra, Debasis

doi:10.1109/inis.2017.16

Cited by 18 publications

(3 citation statements)

References 18 publications

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“…Various error detecting circuits have been discussed in past [30][31][32][33], the most common method is the Hamming Error Detection. R. W. Hamming is the inventor of this approach.…”

Section: Hamming Error Detectionmentioning

confidence: 99%

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices

Khan¹,

Shahid²,

Keshari³

et al. 2023

MMEP

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Error-free communication is crucial for modern electronic devices. Error detection and correction mechanisms are essential to ensure accurate information transmission. With the increasing usage of mobile devices and integrated circuits operating at higher speeds, energy efficiency has become an important design consideration. This study presents carbon nanotube field-effect transistor (CNTFET)-based Hamming Error Detection and Correction circuits and compares them with complementary metal-oxide semiconductor (CMOS)-based counterparts in terms of power efficiency and delay. CNTFETs are more power-efficient and faster than CMOS transistors, making them ideal building blocks for logic circuits. The proposed circuits were simulated using HSPICE. Compared with CMOS circuits, the CNTFET designs consumed less power, had lower delays, and smaller power-delay products. The proposed error detection and correction circuits are suitable for power-efficient and portable systems.

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“…Various error detecting circuits have been discussed in past [30][31][32][33], the most common method is the Hamming Error Detection. R. W. Hamming is the inventor of this approach.…”

Section: Hamming Error Detectionmentioning

confidence: 99%

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices

Khan¹,

Shahid²,

Keshari³

et al. 2023

MMEP

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“…The parity bit is used for error detection through parity data generation (using a parity generator) and checking (using a parity checker). A parity bit (or check bit) is an extra bit (either '1' or '0') that can be associated with a binary string to make 1's count either even or odd [24]. The fundamental basis associated with the designing of parity circuits is that the sum of odd numbers of 1's is always 1, and the sum of even numbers of 1's is always zero.…”

Section: Application To Parity Generator and Checkermentioning

confidence: 99%

High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

Verma,

Sharma,

Pandey

et al. 2023

Preprint

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Strategic detection of an error using a parity generator and parity checker is indispensable and enforces the design engineer to optimize upscale performance. Even advanced modern communication systems can have errors due to losses/noise. This paper brings to light the design of the superior high-speed, low-power 3-bit dynamic parity generator and checker. Two, four, eight, and sixteen-bit XOR gates have been implemented using previous and proposed techniques. The proposed true single-phase dynamic XOR gate builds the parity checker and generator circuits. The proposed dynamic XOR gate, designed 3-bit parity generator, and checker circuits are compared with recently reported techniques. All circuits have been simulated using Cadence Specter on 90nm technology parameters and tested up to 1 GHz of clock frequency. Comparison is made to showcase the superiority of the proposed design in terms of power consumption, propagation delay, PDP (93.8%), EDP (98.8%), number of transistors, the figure of merit, and unity noise gain. This new 3-bit dynamic parity generator and checker would add a colossal perspective for a design engineer.

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“…In Table 8, a reasonable analysis has been formulated and outlined study with 2-dot 1-electron has been assessed with the present effort using 4-dot 2-electron QCA [12,[25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42] considering the figures of cell, extent coverage and energy utilized. From [8], we acquire x = 13 nm and y = 5 nm.…”

Section: Energy and Power Utilization For The Proposed Designmentioning

confidence: 99%

Designing majority gate-based nanoscale two-dimensional two-dot one-electron parity generator and checker for nano-communication

Abdullah-Al-Shafi

Bahar

2019

Int Nano Lett

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At the present time, logic circuits design prototypes with quantum-dot cellular automata (QCA) have been comprehensively researched. The confines of orthodox CMOS technology induce to the breakthroughs of different technologies, one of which is QCA. Thoughtlessly, because of the deficiency of advance assembly support, QCA circuits frequently agonize from several sorts of manufacture shortcomings and variations and, hence, are error prone and defective. QCA technology is forming its aspect due to extreme effectiveness and rapidity with lesser area requirement. This study, a novel architecture of parity generator and checker, is proposed based on two-dot one-electron cells. Parity generator and checker assist in impeccable binary information communication from point to point. With the outlined parity generator and checker circuit, a nano-communication architecture is designed. The designed architecture is rationalized with a competently established standard mathematical operation based on Coulomb's theory. All the outlined design contains a minimum number of cells, extent, and energy compared to existing four-dot two-electron QCA designs. The outlined designs comprehend minimum majority gate and latency. Besides, power depletion by the designs is measured and it is perceived that the total energy and power required to operate these designs are incredibly low.

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Design of Practical Parity Generator and Parity Checker Circuits in QCA

Cited by 18 publications

References 18 publications

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices

High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

Designing majority gate-based nanoscale two-dimensional two-dot one-electron parity generator and checker for nano-communication

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