Design of ternary logic gates and circuits using GNRFETs

Madhuri, Badugu Divya; Sunithamani, S.

doi:10.1049/iet-cds.2019.0427

Cited by 38 publications

(26 citation statements)

References 25 publications

(21 reference statements)

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“…After eliminating the above varieties, 25 papers remain [13, 17, 18, 21, 35–37, 44, 58, 60, 67, 69, 71, 87, 95, 101–108, 131, 132]. However, many of them follow similar structures.…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

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Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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“…After eliminating the above varieties, 25 papers remain [13, 17, 18, 21, 35–37, 44, 58, 60, 67, 69, 71, 87, 95, 101–108, 131, 132]. However, many of them follow similar structures.…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

“…This popularity is mostly because of its high flexibility in threshold adjustment. Other popular technologies are graphene nanoribbon FET [34,47,60,75,76] and memristor [22,23,26,63,[77][78][79][80]. A fusion of two technologies has sometimes been exploited.…”

Section: Statistical Information About Design Techniquesmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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“…Furthermore, with simultaneous consideration of V out =⅔V in , we conclude that both transistors operate in the saturation mode. In this regard, (22) and (24) impose two constraints: i) V Th,n <¾V DD , and ii) |V Th,p |<¼V DD .…”

Section: Th Gs P T H P I N D D T H P D S P I N D D Th P Inmentioning

confidence: 99%

“…Despite several advantages, vulnerability against noise is the Achilles' heel of MVL circuits and systems, especially in today's ongoing reduced voltage. Several ternary [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], quaternary [29][30][31], and quinary [25] inverters with reduced noise margins (NMs) have been presented in the literature. They seriously suffer from unreliability and vulnerability to noise and voltage variation because of their improper Voltage Transfer Characteristic (VTC) shape and nonuniform NMs.…”

Section: Introductionmentioning

confidence: 99%

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Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

2022

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Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFETbased STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.

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GNRFET- and CNTFET-Based Designs of Highly Efficient 22 T Unbalanced Single-Trit Ternary Multiplier Cell

Abbasian,

Aminzadeh,

Taghipour Anvari

2023

Arab J Sci Eng

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Design of ternary logic gates and circuits using GNRFETs

Cited by 38 publications

References 25 publications

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

GNRFET- and CNTFET-Based Designs of Highly Efficient 22 T Unbalanced Single-Trit Ternary Multiplier Cell

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