Design, optimization, and analysis of Si and GaN nanowire FETs for 3 nm technology

Thakur, Rajiv R.; Chaturvedi, Nidhi

doi:10.1088/1361-6641/abfee2

Cited by 8 publications

(4 citation statements)

References 22 publications

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“…Further, increasing the L sp,hk results in improved analog performance whereas the decrease in L sp,hk improves the RF performance. Tri-metal FET 40 3 nm 0.8 61.80 ∼10 6 Si Trigate FET 45 3 nm 0.6 384.17 ∼10 2 Ge SOI FinFET 44 3 nm 0.2 79 ∼10 5 Single Nanowire FET 46 3 nm 0.75 90 ∼10 7 JL SOI V-groove FET 47 3 nm 1.5 74 ∼10 6 Proposed dual-k JL NSFET 3 nm 0.7 62.75 ∼10 9…”

Section: Discussionmentioning

confidence: 99%

Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

Valasa

Tayal²,

Thoutam³

2022

ECS J. Solid State Sci. Technol.

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This manuscript for the first time provides insights on the impact of different spacer materials for the vertically stacked junctionless nanosheet field-effect transistor (JL-NSFET). The analog/radio-frequency (RF) performances of several single-k and dual-k spacers in two approaches namely (1) inner high-k + outer low-k and (2) inner low-k + outer high-k are explored at 3nm gate length. It is noted that the use of TiO2 spacer improves analog performance of the JL-NSFET whereas the usage of SiO2 improves the RF performance of the device when single-k spacer has been used. The intrinsic gain (Av) of the JL-NSFET is improved by ~1.74× with TiO2 as compared to SiO2 spacer. Moreover, it is observed that the dual-k approach with inner high-k + outer low-k combination gives better analog/RF performances compared to inner low-k + outer high-k and single-k spacer combinations. Furthermore, the increase in length (Lsp,hk) of inner high-k spacer length provides improved analog characteristics at the marginal cost of RF performance.

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Section: Discussionmentioning

confidence: 99%

Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

Valasa

Tayal²,

Thoutam³

2022

ECS J. Solid State Sci. Technol.

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“…Along the same line, miniaturization of GaN three-dimensional structures like wires and fins has today become relevant for both electronic and photonic applications in order to profit from the wide-bandgap, the high electron mobility and the excellent thermal stability of the nitride semiconductors in nanoscale devices [2][3][4][5][6][7]. Specifically, ultrathin GaN nanowires (NWs) with diameters 20 nm are beneficial for achieving ultrafast switching in field-effect transistors [8,9], they can elastically relax large amounts of epitaxial strain [10][11][12][13], and they host dielectrically confined excitons up to room temperature [14]. If arranged deterministically on the substrate surface, such NW arrays can principally form photonic cavities [15] and they ease the parallel contacting of many single NWs [16].…”

Section: Introductionmentioning

confidence: 99%

A route for the top-down fabrication of ordered ultrathin GaN nanowires

et al. 2023

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We introduce a facile route for the top-down fabrication of ordered arrays of GaN nanowires with aspect ratios exceeding 10 and diameters below 20 nm. Highly uniform thin GaN nanowires are first obtained by lithographic patterning a bilayer Ni/SiNx hard mask, followed by a combination of dry and wet etching in KOH. The SiNx is found to work as an etch stop during wet etching, which eases reproducibility. Arrays with nanowire diameters down to (33 ± 5) nm can be achieved with a uniformity suitable for photonic applications. Next, a scheme for digital etching is demonstrated to further reduce the nanowire diameter down to 5 nm. However, nanowire breaking or bundling is observed for diameters below ≈ 20 nm, an effect that is associated to capillary forces acting on the nanowires during sample drying in air. Explicit calculations of the nanowire buckling states under capillary forces indicate that nanowire breaking is favored by the incomplete wetting of water on the substrate surface during drying. The observation of intense nanowire photoluminescence at room-temperature indicates good compatibility of the fabrication route with optoelectronic applications. The process can be principally applied to any GaN/SiNx nanostructures and allows regrowth after removal of the SiNx mask.

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“…Along the same line, miniaturization of GaN three-dimensional structures like wires and fins has today become relevant for both electronic and photonic applications [2][3][4][5][6][7]. Specifically, ultrathin GaN nanowires (NWs) with diameters ≤ 20 nm are beneficial for achieving ultrafast switching in field-effect transistors [8,9], they can elastically relax large amounts of epitaxial strain [10-12], and they host dielectrically confined excitons up to room temperature [13]. If arranged deterministically on the substrate surface, such NW arrays can principally form photonic cavities [14] or interconnects [15].…”

Section: Introductionmentioning

confidence: 99%

A route for the top-down fabrication of ordered ultrathin GaN nanowires

Oliva¹,

Kaganer²,

Pudelski³

et al. 2022

Preprint

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Ultrathin GaN nanowires (NWs) are attractive to maximize surface effects and as building block in high-frequency transistors. Here, we introduce a facile route for the top-down fabrication of ordered arrays of GaN NWs with aspect ratios exceeding 10 and diameters below 20 nm. Highly uniform thin GaN NWs are first obtained by using electron beam lithography to pattern a Ni/SiN x hard mask, followed by dry etching and wet etching in hot KOH. The SiN x is found to work as an etch stop during wet etching in hot KOH. Arrays with NW diameters down to (33 ± 5) nm can be achieved with a yield exceeding 99.9 %. Further reduction of the NW diameter down to 5 nm is obtained by applying digital etching which consists in plasma oxidation followed by wet etching in hot KOH. The NW radial etching depth is tuned by varying the RF power during plasma oxidation. NW breaking or bundling is observed for diameters below ≈ 20 nm, an effect that is associated to capillary forces acting on the NWs during sample drying in air. This effect can be principally mitigated using critical point dryers. Interestingly, this mechanical instability of the NWs is found to occur at much smaller aspect ratios than what is predicted for models dealing with macroscopic elastic rods. Explicit calculations of buckling states show an improved agreement when considering an inclined water surface, as can be expected if water assembles into droplets. The proposed fabrication route can be principally applied to any GaN/SiN x nanostructures and allows regrowth after removal of the SiN x mask.

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Design, optimization, and analysis of Si and GaN nanowire FETs for 3 nm technology

Cited by 8 publications

References 22 publications

Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

Performance Evaluation of Spacer Dielectric Engineered Vertically Stacked Junctionless Nanosheet FET for Sub-5 nm Technology Node

A route for the top-down fabrication of ordered ultrathin GaN nanowires

A route for the top-down fabrication of ordered ultrathin GaN nanowires

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