Design tradeoffs in stall-control circuits for 600 MHz instruction queues

Fischer, Tim; Leibholz, D.

doi:10.1109/isscc.1998.672448

Cited by 4 publications

(2 citation statements)

References 3 publications

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“…New instructions can enter the issue queue when there are four or more available queue slots, and new instructions can enter the floating-point queue when there are enough available queue slots. 9 Instruction retire and exception handling…”

Section: Out-of-order Issue Queuesmentioning

confidence: 99%

The Alpha 21264 microprocessor

1999

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Section: Out-of-order Issue Queuesmentioning

confidence: 99%

The Alpha 21264 microprocessor

1999

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“…The ReLaSch processor, as well as the IO and OoO reference processors are based on the 21264 processor. Several papers and manuals related with the Alpha ISA and the 21264 processor have been used as reference during the research of this thesis [59,15,18,60,61,62,63].…”

Section: Common Register Filementioning

confidence: 99%

Reusing cached schedules in an out-of-order processor with in-order issue logic

Pérez¹

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Modern processors use out-of-order processing logic to achieve high performance in Instructions Per Cycle (IPC) but this logic has a serious impact on the achievable frequency. In order to get better performance out of smaller transistors there is a trend to increase the number of cores per die instead of making the cores themselves bigger. Moreover, for throughput-oriented and server workloads, simpler in-order processors that allow more cores per die and higher design frequencies are becoming the preferred choice. Unfortunately, for other workloads this type of cores result in a lower single thread performance. There are many workloads where it is still important to achieve good single thread performance. In this thesis we present the ReLaSch processor. Its aim is to enable high IPC cores capable of running at high clock frequencies by processing the instructions using simple superscalar in-order issue logic and caching instruction groups that are dynamically scheduled in hardware after commit, that is, out of the critical path and only when really needed. Objective This thesis has several research goals: • Show that the dynamic scheduler of a conventional out-of-order processor does a lot of redundant work because it ignores the repetitiveness of code. • Propose a complete superscalar out-of-order architecture that reduces the amount of redundant work done by creating the schedules once in dedicated hardware, storing them in a cache of schedules and reusing the schedules as much as possible. • Place the scheduler out of the critical path of execution, which should be enabled by the reduction of work that it must do. Thus, the execution path of our proposed processor can be simpler than that of a conventional out-of-order processor. Proposal and results We present the \textbf{ReLaSch} processor, named after Reused Late Schedules, in which the creation of issue-groups is removed from the critical path of execution and uses a simple and small in-order issue logic. It just wakes-up and selects the instructions of a single issue-group each cycle, instead of processing the instructions of a whole issue queue. A new logic at the end of the conventional pipeline schedules the committed instructions. The new scheduler can be complex since it is not in the critical path of execution. The schedules are cached and whenever it is possible an rgroup is read and its instructions executed. The schedules are reused, lowering the pressure on the scheduling logic. In some cases, the ReLaSch processor is able to outperform a conventional out-of-order processor, because the post-commit scheduler has a broader vision of the code. For instance, while ReLaSch can schedule together two independent instructions that are distant in the code, a conventional out-oforder processor only issues them in the same cycle if both are in-flight. The ReLaSch processor predicts the branch targets, memory aliases and latencies at scheduling time, out of the critical path. The prediction is based on the most recent executions at scheduling time. Furthermore, most of the register renaming process is performed by the scheduler and is removed from the execution pipeline. Our experiments show that ReLaSch has the same average IPC as our reference out-of-order processor and is clearly better than the reference inorder processor (1.55 speed-up). In all cases it outperforms the in-order processor and in 23 benchmarks out of 40 it has a higher IPC than the reference out-of-order processor.

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Reusing cached schedules in an out-of-order processor with in-order issue logic

Palomar

JuanJ

Navarro

2009

2009 IEEE International Conference on Computer Design

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Abstract-The complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue logic belongs to just 13% of the total different groups issued: the issue logic of an out-of-order processor is constantly re-discovering what it has already found. To benefit from the repetitive nature of instruction issue, we move the scheduling logic after the commit stage, out of the critical path of execution. The schedules created there are cached and reused to feed a simple in-order issue logic, that could result in a higher frequency design. We present the complete design of our ReLaSch processor, that achieves the same average IPC than a conventional out-of-order processor, and a 1.56 speed-up over the IPC of an in-order processor. We actually surpass the out-of-order IPC in 23 out of 40 SPEC benchmarks, mainly because the broader vision of the code after the commit stage allows creating better schedules.

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Design tradeoffs in stall-control circuits for 600 MHz instruction queues

Cited by 4 publications

References 3 publications

The Alpha 21264 microprocessor

The Alpha 21264 microprocessor

Reusing cached schedules in an out-of-order processor with in-order issue logic

Reusing cached schedules in an out-of-order processor with in-order issue logic

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