Designing a one-bit coplanar QCA ALU using a novel robust area-efficient three-input majority gate design

Abstract

Quantum-dot Cellular Automata (QCA) which is a suitable alternative to conventional CMOS technology is susceptible to some defects in chemical synthesis and deposition phases of circuit fabrication. Besides, the majority gate is one of the most important primary gates for designing digital circuits in this emerging technology. Designing a faulttolerant majority gate is one of the hot topics in QCA technology. Most previous works tried to improve the majority gate reliability by increasing the number of QCA cells which resulted in occupying more area. In this paper we propose a novel area-efficient three-input majority gate which can tolerate the single-cell omission and extra-cell deposition defects by 86% and 75%, respectively. The proposed majority gate consists of 11 simple QCA cells with 0.006 µm 2 and 1.62 e-002 MeV area and energy consumption, respectively. A complete fault tolerance analysis for our proposed majority gate against cell omission, extra-cell deposition, and cell displacement and misalignment defects is also provided. We design a fault-tolerant coplanar fulladder/fullsubtractor and a two-to-one multiplexer using the proposed majority gate and compare it with the same previous works. Simulation results from QCADesigner 2.0.3 and QCADesigner-E show that in all cases our proposed robust circuits can reduce the area consumption. Finally, we implement a fault tolerant coplanar one-bit ALU using the proposed circuits that can perform four logical and mathematical operations.

Design and implementation of an 8-bit ALU based on verilog HDL

“…The ALU processes the input through the arithmetic units and the logical units, and outputs the results. 1 is the operation code of the ALU and the operation instructions corresponding thereto respectively, the 4-bit operation code were used to define the operation type [5]. Code from 0000 to 0011 are arithmetic calculation, code 0000 corresponds to addition for the addition calculation of the ALU, code 0001 to subtraction for the ALU subtraction calculation, code 0010 for the multiplication for the ALU multiplication, and code 0011 to division for the division calculation of the ALU.…”