Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations

Abstract

Implementing aliasing-free (zero-aliasing) space compressors for built-in self-testing of very large scale integration circuits and systems is of great significance, especially in view of the technological paradigm shift in recent years from system-on-board to system-on-chip design. This paper investigates and provides new approach to realizing aliasing-free elementary-tree space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test, the paper introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to twoinput AND/NAND and XOR/XNOR logic. The process is illustrated in the paper with details of synthesis of space compressors for the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using fault simulation programs ATALANTA, FSIM and HOPE, exemplifying the relevance of the technique from the standpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, making it thus a logical choice in commercial design environments. Keywords-Built-in self-testing in very large scale integration, cores-based system-on-chips, fault detection compatibility and conditional fault detection compatibility, space compression.This full text paper was peer-reviewed at the direction of IEEE Instrumentation and Measurement Society prior to the acceptance and publication.978-1-4799-6144-6/15/$31.00 ©2015 IEEE