Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Nikolić, Stefan; Zgheib, Grace; Ienne, Paolo

doi:10.1145/3501802

Cited by 4 publications

(3 citation statements)

References 30 publications

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“…These solutions are very popular at present for the implementation of various projects. This fact is confirmed by the analysis of the literature [22][23][24][25][26][27][28].…”

supporting

confidence: 67%

Improving Hardware in LUT-Based Mealy FSMs

2022

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The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. The interstate transitions are represented by output collections generated during two adjacent cycles of FSM operation. To avoid doubling the number of variables encoding of COs, two registers are used. The first register keeps a code of CO produced in the current cycle of operation; the code of a CO produced in the previous cycle is kept in the second register. There is given a synthesis example with applying the proposed method. The results of the research are shown. The research is conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows reducing the hardware compared with such known methods as auto and one-hot of Vivado, and JEDI. Additionally, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding of COs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 7.21% without significant reduction in the performance. Our approach loses in terms of power consumption (on average 9.62%) and power–time products (on average 10.44%). The gain in LUT counts and area–time products increases with the increase in the numbers of FSM states and inputs.

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“…These solutions are very popular at present for the implementation of various projects. This fact is confirmed by the analysis of the literature [22][23][24][25][26][27][28].…”

supporting

confidence: 67%

Improving Hardware in LUT-Based Mealy FSMs

2022

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“…These options include the utilization of Lookup Tables (LUTs) or adopting unconventional methods such as online arithmetic. The LUT-based implementations on FPGAs provide a favorable equilibrium among flexibility, efficiency, programmability, and speed, rendering them a highly recommended option for function implementation on FPGA platforms [28,29].…”

Section: Fuzzifiermentioning

confidence: 99%

A Hardware Realization Framework for Fuzzy Inference System Optimization

Gorgin,

Karvandi,

Moghari

et al. 2024

Electronics

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Fuzzy inference systems (FISs) are a key focus for decision-making in embedded systems due to their effectiveness in managing uncertainty and non-linearity. This study demonstrates that optimizing FIS hardware enhances performance, efficiency, and capabilities, improving user experience, heightened productivity, and cost savings. We propose an ultra-low power FIS hardware framework to address power constraints in embedded systems. This framework supports optimizations for conventional arithmetic and Most Significant Digit First (MSDF) computing, ensuring compatibility with MSDF-based sensors. Within the MSDF-computing FIS, fuzzification, inference, and defuzzification processes occur on serially incoming data bits. To illustrate the framework’s efficiency, we implemented it using MATLAB, Chisel3, and Vivado, starting from high-level FIS descriptions and progressing to hardware synthesis. A Scala library in Chisel3 was developed to connect these tools seamlessly, facilitating design space exploration at the arithmetic level. We applied the framework by realizing an FIS for autonomous mobile robot navigation in unknown environments. The synthesis results highlight the superiority of our designs over the MATLAB HDL code generator, achieving a 43% higher clock frequency, and 46% and 67% lower resource and power consumption, respectively.

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“…Lin et al [28], [29] proposed efficient delay model and timing-driven placement considering clock constraints. Nikolić et al [30] proposed an efficient ILP-based detailed placer which moves a carefully selected subset of LUTs to efficiently improve timing.…”

Section: A Related Workmentioning

confidence: 99%

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Liang¹,

Chen²,

Zhao³

et al. 2022

Preprint

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To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous analytical placers. Moreover, general timing-driven placement algorithms are facing challenges when handling real-world application design and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an open-source comprehensive timing-driven Analytical Mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the timing quality of the placement, standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including a simple but effective timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timingdriven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools.

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Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Cited by 4 publications

References 30 publications

Improving Hardware in LUT-Based Mealy FSMs

Improving Hardware in LUT-Based Mealy FSMs

A Hardware Realization Framework for Fuzzy Inference System Optimization

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

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