Detecting delay flaws by very-low-voltage testing

Abstract

Timing failures occur when the delay of the manufactured component is different from the designed delay [6]. This paper considers the effectiveness of VLV testing in detecting timing failures. A circuit has a delay flaw (non-operational delay fault) if there is a timing failure but the circuit continues to work at the designed speed [6] [7]. Flaw coverage of a delay flaw is the range of the attribute of a flaw that can be detected by a test, such as the range of the resistance of a short that can be detected by a test [2]. We will first discuss the failure

Experimental results for IDDQ and VLV testing

“…There were several test escapes when testing at 2.5V while all CUT VLV-only failures failed at 1.7V. This result supports the supply voltage proposed for VLV testing in [9] and [10]. Two CUT VLV-only failures had IDDQ measurements smaller than 3µA.…”

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

“…Similar simulations were performed with SOI models using the same tests and the results generally agree with the conclusions drawn in the previous report. In SOI technology, the supply voltage should be no higher than 2.25 times the threshold voltage to provide comparable flaw coverage to that reported in [17], as illustrated in Fig. 10.…”

“…The sensitivity of a transistor's performance to fluctuations increases as is lowered in either bulk or SOI technology and this is one of the motivations for employing very low voltage (VLV) testing [17]- [19]. This increased sensitivity can be seen intuitively from the classic drive current equation shown as (1), where the parenthetic term approaches zero as approaches -given that is bound by .…”

“…In [17], a methodology was described for 0.8-and 0.6-m bulk technology for the selection of an effective for VLV testing. The range of was established by considering the tradeoffs between flaw coverage (resistance of defect detected), test time, and noise margins.…”

“…In [17], two sets of tests were simulated: 1) a NAND gate with a gate oxide short and 2) a metal short between two outputs of inverters in separate inverter chains. Acceptable flaw coverage (resistance detected) in the case of both gate-oxide shorts and metal-resistive shorts, was targeted to be at least 5 K , which represents the vast majority of both of these defect types.…”