Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP

Tariq, M.F.; Baltaci, Yusuf; Horseman, Tony R; Butler, M.R.G.; Nix, AR

doi:10.1109/icc.2002.996908

Cited by 22 publications

(7 citation statements)

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“…The platform must incorporate enough flexibility, so that all choices of interest can be tried for parameters to be optimized. In [14] and [15] two prototyping platforms are presented in the context of OFDM systems. In this paper we propose an FPGA implementation of a reconfigurable OFDM-based physical layer and a multi-purpose validation test bed.…”

Section: Introductionmentioning

confidence: 99%

Beyond 3G wireless communication system prototype

Dassatti

Zezza

Nicola

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Modern wireless systems have to achieve very high data rates over noisy channels. Channel codes are usually used to guarantee reliable communication, but validating a system with extremely low Bit Error Rate (BER) requires the simulation of a huge number of samples. The simulation complexity furtherly increases if we want to take into account the joint effect of channel codes and complex modulation techniques, such as Orthogonal Frequency Division Multiplexing (OFDM), over multi-path fading channel. The use of software simulators to evaluate system performance in several scenarios may result in unacceptably long times and a reconfigurable hardware prototyping environment may be an effective solution. This paper describes the implementation of a complete real-time, fully digital, flexible high performance hardware/software prototype for beyond 3G wireless communications. The transmitter/receiver chain includes several innovative characteristics: Serial Concatenated Convolutional Codes (SCCC) Turbo Encoder/Decoder, adaptive OFDM modulation, versatile multiple user access scheme and a sophisticated, real-time power control.Optimal choices for partitioning and internal data representation have been described as well as internal architecture and measurement environment. Our programmable prototype ensures high flexibility and speedup of more than 4000 times compared with the software version.

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Section: Introductionmentioning

confidence: 99%

Beyond 3G wireless communication system prototype

Dassatti

Zezza

Nicola

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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“…For example, Figure 1 shows the baseband processing of the WLAN OFDM (orthogonal frequency-division multiplexing) modem system [3]. The binary input data is scrambled and encoded by a standard rate 1/2 convolutional encoder.…”

Section: Introductionmentioning

confidence: 99%

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

Jeong

Sunwoo

2005

EURASIP J. Adv. Signal Process.

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This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about for scrambling, convolutional encoding, and interleaving compared with existing DSPs.

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“…In multicarrier modulation, such as OFDM (Orthogonal Frequency-Division Multiplexing) [4, 61 and discrete multitone (DMT) 171, data symbols are 'transmitted in parallel on multiple subcarriers. Multicarrier modulation data communication systems and have been selected for the wireless local area network (WLAN) [8], digital audio broadcasting (DAB) [9], digital video broadcasting (DVB) [IO], very high-speed digital subscriber line (VDSL) [ OFDM modem systems in these standards consist of several blocks, such as a convolutional encoder, a scrambler, a puncturing, an interleaver and FFT. Each block requires different computation cycles.…”

Section: Introductionmentioning

confidence: 99%

Novel DSP architecture for OFDM modem systems

Lee

Jeong

Sunwoo

et al.

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682)

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This paper presents application-specific instructions and DSP architecture for OFDM algorithms The proposed instructions calculate a butterfly within two cycles and reduce computation cycles of scrambling, convolutional encoding, and timing synchronization. Tbe proposed DSP employs a Data Processing Unit (DPU) supporting the special instructions and an FFT Address Generation Unit (FAGU) automatically calculating the butterfly input data addresses. The proposed DSP has been synthesized using the SEC 0.18pni standard cell library and has a smaller area than commercial DSP chips. Performance comparisons show that the number of clock cycles improves over 10% for FFT computation and the size of the DPU decreases about 30% compared with Camel DSP.

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Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP

Cited by 22 publications

References 1 publication

Beyond 3G wireless communication system prototype

Beyond 3G wireless communication system prototype

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

Novel DSP architecture for OFDM modem systems

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