Diagnosis of scan path failures

Edirisooriya, S.; Edirisooriya, G.

doi:10.1109/vtest.1995.512645

Cited by 98 publications

(32 citation statements)

References 2 publications

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“…Solutions include adding extra on-chip hardware [10][11][12] or generating additional diagnostic test patterns [13,14]. Although effective, these approaches are intrusive w.r.t.…”

Section: Related Prior Workmentioning

confidence: 99%

On Scan Chain Diagnosis for Intermittent Faults

Adolfsson

Siew

Marinissen

et al. 2009

2009 Asian Test Symposium

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Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

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“…Solutions include adding extra on-chip hardware [10][11][12] or generating additional diagnostic test patterns [13,14]. Although effective, these approaches are intrusive w.r.t.…”

Section: Related Prior Workmentioning

confidence: 99%

On Scan Chain Diagnosis for Intermittent Faults

Adolfsson

Siew

Marinissen

et al. 2009

2009 Asian Test Symposium

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“…The diagnostic technique is quite similar to that of [22], but in order to reduce the impact of X states, one has to increase the number of outputs. Finally, various specialized techniques have been proposed to diagnose scan chain failures [7], [11], [14], [17], [24]. This paper presents a novel indirect fault diagnosis technique that takes advantage of a very simple compaction scheme and can be used in high-volume production diagnosis.…”

Section: Introductionmentioning

confidence: 99%

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

et al. 2011

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This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal-spatial and time-signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

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“…Several techniques for diagnosis of hold time failures in scan chains [3][4][5][6] as well as in generic short logic paths [7] are proposed. These techniques are applied for buffer insertion, i.e.…”

Section: Introductionmentioning

confidence: 99%

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

Neuberger¹,

Wirth²,

Kastensmidt³

et al. 2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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Abstract. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we investigate the variability of flip-flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ~1ps is used to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to-die variations of hold time violations are measured in various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12-16%. Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm. Normality tests to check if the variability follows a normal Gaussian distribution are also presented.

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Diagnosis of scan path failures

Cited by 98 publications

References 2 publications

On Scan Chain Diagnosis for Intermittent Faults

On Scan Chain Diagnosis for Intermittent Faults

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

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