Digital Equalization for Cancellation of Noise-Like Interferences in Adaptive Spatial Filtering

Mandal, Amritakar; Mishra, Rajesh

doi:10.1007/s00034-016-0324-5

Cited by 9 publications

(3 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is a compromise between computing accuracy, latency, and FPGA chip occupation. The approaches presented in [27,28,29] should improve accuracy and latency of the proposed structure. In our future work, we will focus on a smaller chip occupation and a lower power consumption, as well.…”

Section: Resultsmentioning

confidence: 99%

“…The latency of the CORDIC algorithm depends on the number of rotation building blocks and number of iterations performed by the rotation building block [29]. In the example presented in Section 4, there are three serial blocks of seven rotation building blocks.…”

Section: Discussionmentioning

confidence: 99%

“…The vector element of row r + 1, y 1 r + 1 (n), moves up to row r and only the new vector elements of (r + 1)th and (r + 2)th rows are determined. Subsequently, rotations R r − 1 T , R r T …, until the rotation R 1 T are applied (see (29)) . Finally, (29) can be rearranged as follows: Fig.…”

Section: Implementation Algorithmmentioning

confidence: 99%

See 2 more Smart Citations

Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures

Poczekajło

Wawryn

2018

IET signal process.

View full text Add to dashboard Cite

A novel algorithm for the realisation of an orthogonal digital system performing three-dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state-space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field-programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct-form structure consisting of adders, multipliers, and delay elements.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%