Digital signal resampling device for self-organizing networks

Voronov, Egor; Solodkov, Alexey; Belousov, Egor

doi:10.1109/itecha.2015.7317386

Cited by 2 publications

(1 citation statement)

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“…The second method is instead limited to decimation factors that are equal to L M , where L and M are integers. Both methods counteract aliasing effects by means of low-pass filtering operations, which are implicit in the interpolation algorithm, and explicit in the processing scheme of polyphase filters [12][13][14][15]. In fact, the use of an interpolation function is equivalent to filtering the signal with a filter characterized by a frequency response where the number of taps is equal to the number of points used in interpolation.…”

Section: Introductionmentioning

confidence: 99%

Digital Circuit for Seamless Resampling ADC Output Streams

D’Arco

Napoli

Zacharelos

2020

Sensors

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Fine resolution selection of the sample rate is not available in digital storage oscilloscopes (DSOs), so the user has to rely on offline processing to cope with such need. The paper first discusses digital signal processing based methods that allow changing the sampling rate by means of digital resampling approaches. Then, it proposes a digital circuit that, if included in the acquisition channel of a digital storage oscilloscope, between the internal analog-to-digital converter (ADC) and the acquisition memory, allows the user to select any sampling rate lower than the maximum one with fine resolution. The circuit relies both on the use of a short digital filter with dynamically generated coefficients and on a suitable memory management strategy. The output samples produced by the digital circuit are characterized by a sampling rate that can be incoherent with the clock frequency regulating the memory access. Both a field programmable gate array (FPGA) implementation and an application specific integrated circuit (ASIC) design of the proposed circuit are evaluated.

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Section: Introductionmentioning

confidence: 99%