2020
DOI: 10.1007/s11664-020-08353-x
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Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions

Abstract: It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas comp… Show more

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