Divide-by-8 phase detector MMIC for PLL-based carrier recovery in E-band communication

Messinger, T.; Müller, D.; Antes, J.; Wagner, Stefan; Tessmann, A.; Kallfass, Ingmar

doi:10.1109/gemic.2015.7107797

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Cited by 7 publications

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“…Numerous research results of CPPLL have been published, such as [9][10][11][12][13][14]. In [11], a CPPLL is realized using a 65 nm Si CMOS process.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Zhao

Zhang

et al. 2022

Sensors

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This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

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“…Numerous research results of CPPLL have been published, such as [9][10][11][12][13][14]. In [11], a CPPLL is realized using a 65 nm Si CMOS process.…”

Section: Introductionmentioning

confidence: 99%