Drain Disturb Relaxation by Substrate bias Selecting Scheme for Sector Erase Flash Memory with Conventional Single Stacked Gate Cell Structure

Abstract

5-q37, FACS IMILE: (Q7 436) 5-277 4 l.Introduction Recently high density flash memory has been expected to replace the external mass storage device market d computers. For this application, fast random access, low power consumption, and small erase unit size are required.