DRAM selection and configuration for real-time mobile systems

Gomony, Manil Dev; Weis, Christian; Åkesson, Benny; Wehn, Norbert; Goossens, Kees

doi:10.1109/date.2012.6176432

Cited by 14 publications

(14 citation statements)

References 19 publications

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“…As studied before by Shah et al [12], an analytical analysis method achieves better results in latency estimation if compared to a method based on abstraction of data communication, as the latency-rate method [3]. Even based on the worst case, the analytical analysis of delays is preferred than the use of temporal estimation [12].…”

Section: Related Workmentioning

confidence: 96%

“…Because processing elements can have a timing variant data access behavior, adaptive priorities control and client access preemption for memory access has benefits to the memory subsystem, as presented before in [8,6]. Memory system model and design are widely explored in recent works [1,2,7,8,6,12,3,4,15,16,17] and show the state-of-the-art in the area of memory systems design.…”

Section: Introductionmentioning

confidence: 98%

See 1 more Smart Citation

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Bonatto

Negreiros

Pereira

et al. 2014

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

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Memory subsystem is a major concern in the design of multimedia systems and the memory performance may become the bottleneck for the overall processing performance. This work presents a memory subsystem implementation with adaptive control for access to shared memory in multimedia Systems-on-Chip (SoC). A memory-centric design approach is used to implement the memory subsystem for the purpose of meet bandwidth and deadline requirements of the heterogeneous processing elements. A latency-based model is obtained based on the Worst-Case Response Time (WCRT) criterion. In the presented approach, an adaptive arbiter is designed and implemented to control memory access requests targeting to comply with clients' deadline requirements managing data latency of accesses. Also, an algorithmic implementation of the adaptive arbitration control is presented and evaluated. This paper presents hardware implementation results for the proposed memory subsystem with an adaptive arbiter control. Our proposal of simple estimation of WCRT leads to a hardware implementation with low latency calculation of the system limits imposed to clients. This way the proposed adaptation approach can be implemented at run-time.

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Section: Related Workmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 98%

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Bonatto

Negreiros

Pereira

et al. 2014

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

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“…Memory-centric architecture of an HD video and graphics processing system. up to 16 memory channels, as it will be a valid multichannel memory configuration in the near future [HMC 2014]. It can be seen that the heuristic algorithm runs much faster (the First-fit and Interleave-all algorithms also run in less than a second) than the optimization tool and is required to scale to future needs.…”

Section: Computation Time Comparisonmentioning

confidence: 99%

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Gomony

Åkesson

Goossens

2015

ACM Trans. Embed. Comput. Syst.

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Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. We demonstrate the real-time guarantees on bandwidth and latency provided by our multichannel memory controller architecture by experimental evaluation. Furthermore, we compare the performance of the mapping problem formulation in a solver and the heuristic algorithm against two existing mapping algorithms in terms of computation time and mapping success ratio. We show that an optimal solution can be found in 2 hours using the solver and in less than 1 second with less than 7% mapping failure using the heuristic for realistically sized problems. Finally, we demonstrate configuring a Wide IO DRAM in a high-definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of this work. ACM Reference Format:Manil Dev Gomony, Benny Akesson, and Kees Goossens. 2015. A real-time multichannel memory controller and optimal mapping of memory clients to memory channels.

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“…[44] compares several (asynchronous) DRAM architectures and considers SDRAM as one special case within this family, but does not zoom in further. In [45], the focus lies on selecting a suitable memory for a design rather than giving a general performance overview, and it only considers LPDDRx memories.…”

Section: Related Workmentioning

confidence: 99%

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Goossens

Chandrasekar

Åkesson

et al. 2016

IEEE Trans. Comput.

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Abstract-Real-time safety-critical systems should provide hard bounds on an applications' performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers' performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.

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DRAM selection and configuration for real-time mobile systems

Cited by 14 publications

References 19 publications

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

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