Dual port ram based layered decoding for Multi Rate Quasi-Cyclic LDPC codes

Abstract

This paper presents a generic RAM based FPGA architecture for decoding of Multi Rate Quasi-Cycling LDPC codes. RAM based decoding enables us to reduce permutation networks into simple address controllers. Moreover, utilizing Block RAMs with various aspect ratios in an FPGA provides flexibility ranging from area driven compact designs to fully parallelized high throughput designs. Utilizing the read-first property of the RAMs, the proposed design efficiently exploits the dual port Block RAM resources by accessing all the four ports at the same time. Such facilities of recent FPGA devices have been combined with the well known layered decoding algorithm with non-linearly mapped Min-Sum approximation in order to obtain area efficient yet high throughput decoders. The proposed decoder architecture has been verified on Xilinx XC7Z020 FPGA device for IEEE 802.16e Wimax LDPC codes. 340Mbps of information throughput has been observed at an operating frequency of 150MHz.

A Survey on FEC Techniques for Industrial Wireless Communications

“…Broulim et al [151] and Balatsouka-Stimming et al [152] offer an implementation of MIN-SUM with full parallel decoding. In the case of BP, full parallel decoding is proposed in the works of Li et al [153], Yesil et al [154] and Yen et al [155]. Other MIN-SUM implementations in which semi-parallel decoding is proposed are [156]- [158], while for BP case there is the proposal of [159].…”