Dual Si3N4 Charge Trapping Layer (SONNOS) Nonvolatile Memory With Ultra-Thin Body Trench Poly-Si Junctionless FET for 3D NAND Applications

Abstract

This work presents the structure Junctionless FinFET (JLFinFET) based on ultra-thin body (UTB) with double stacked Si3N4 charge trapping layer (NN-CTL) Si-SiO2-Si3N4-Si3N4-SiO2-Si (SONNOS) nonvolatile memory (NVM). The device shows excellent transistor performances including steep sub-threshold swing (SS) of 76 mV/dec, favorable Vth, and high Ion/Ioff ratio (>107). For n-channel device, it shows excellent memory characteristics, high program/erase (P/E) performance, good endurance (>104 cycles) and an excellent 95∼99% electron retention at 85°C for 10 years.