Dual Split-Merge: A high throughput router architecture for FPGAs

Helal, Khaled A.; Attia, Sameh; Fahmy, Hossam A. H.; Ismail, Tawfik; Ismail, Yehea; Mostafa, Hassan

doi:10.1016/j.mejo.2018.08.013

Cited by 6 publications

(5 citation statements)

References 3 publications

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“…It depends on the level of configurability of the available building blocks Ad hoc approaches [54]- [72] No dependency on fixed or flexible architectures…”

Section: Motivation For a New Design Methodologymentioning

confidence: 99%

“…There are modular designs where the router internally handles each dimension of the NoC independently [54]- [59], shared-buffers approaches [60]- [62], path-sensitive with decomposed crossbar designs [63]- [65], bufferless approaches [70]- [72], and other design alternatives such as decentralized structure based on rings [66], pre-configured paths [67], hybrid packet/circuit switching [68], and crossbar folding with marching memory buffers [69].…”

Section: Ad Hoc Approachesmentioning

confidence: 99%

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A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

2023

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R. PARRA-MICHEL was born in Guadalajara, Mexico, in 1973. He received the B.Sc. degree in electronics and communications from the University of Guadalajara, in 1996, the M.Sc. degree in electrical engineering specializing in communications from CINVESTAV-IPN, Guadalajara, in 1998, and the Ph.D. degree in electrical engineering specialized in digital signal processing for communications from CINVESTAV-IPN, Mexico City, in 2003. He has collaborated with several companies and institutions either in academic or technology projects, such as Siemens, Lucent, Mabe, Mixbaal, Hewlett-Packard, and Intel. He is currently the Director of Guadalajara Unit, CINVESTAV-IPN, and the Head of the Wireless Communication Group. His research interests include modeling, simulation, estimation and equalization of communication channels, digital implementation of DSP algorithms for communication systems and on-chip networks.

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“…It depends on the level of configurability of the available building blocks Ad hoc approaches [54]- [72] No dependency on fixed or flexible architectures…”

Section: Motivation For a New Design Methodologymentioning

confidence: 99%

Section: Ad Hoc Approachesmentioning

confidence: 99%

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

2023

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“…Split-merge design 14 is based on split and merge crossbar in order to provide higher operation frequency compared with CONNECT. DSM 15 is a high-throughput…”

Section: Related Workmentioning

confidence: 99%

“…Split–merge design 14 is based on split and merge crossbar in order to provide higher operation frequency compared with CONNECT. DSM 15 is a high‐throughput FPGA‐based router with dual split–merge units. DSM divides the router into two separated routers for increasing the operating frequency and the network throughput.…”

Section: Related Workmentioning

confidence: 99%

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A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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