Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing

Hossain, Shazzad; Savidis, Ioannis

doi:10.1016/j.mejo.2020.104801

Cited by 4 publications

(2 citation statements)

References 19 publications

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“…where L N2 refers to the channel length of M N2 and L N1 = L N2 = L. Also, W N2 , V gN2 and V T0N2 are the width, gate to source and threshold voltage, respectively, of M N2 . Substituting V gN2 and V T0N1 = V T0N2 = V T0N in (7) gives, ( ) ( ) ( )…”

Section: Analytical Model For Delaymentioning

confidence: 99%

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An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

Kumar¹,

Mondal²

2023

RADIOENGINEERING

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Digital subsystem prefers CMOS process, but it is difficult to manage speed and average power (P avg ) trade-off in each era with power supply voltage (V dd ) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block of a SerDes, namely, the latch. However, available CML circuits consume significant P avg and suffer from rapid input slewing. Typically, fast switching inputs enable current flow to effective supply voltage V P and overcharges output. In fact, V P is different than externally applied V dd and oscillates with time as and when an abrupt current is drawn. This affects delay t d and introduces jitter. The topic presents a new latch for SerDes interface using a new current steering circuit and coupled to a power delivery network (PDN). The significant point is to attain an almost constant t d in comparison to conventional designs while the V dd changes. The post-layout results at 0.09-μm CMOS and 1.1 V V dd indicate that the P avg and t d are 339.5 µW and 61.9 ps, respectively, at 27°C. Surprisingly, the t d variation is noted to be minimum and the power supply noise induced jitter is around 1.5 ns when V P close to the circuit varies due to sudden current.

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Section: Analytical Model For Delaymentioning

confidence: 99%

“…This happens due to process, voltage and temperature (PVT). In a SerDes other circuits are included along with latch while connected to a common VP and all do not operate at the same time [7]. As some circuits are suddenly turned on, an abrupt current is drawn.…”

Section: Introductionmentioning

confidence: 99%