Dynamic energy management for chip multi-processors under performance constraints

Abstract

We introduce a novel algorithm for dynamic energy management (DEM) under performance constraints in chip multi-processors (CMPs). Using the novel concept of delayed instructions count, performance loss estimations are calculated at the end of each control period for each core. In addition, a Kalman filtering based approach is employed to predict workload in the next control period for which voltage-frequency pairs must be selected. This selection is done with a novel dynamic voltage and frequency scaling (DVFS) algorithm whose objective is to reduce energy consumption but without degrading performance beyond the user set threshold. Using our customized Sniper based CMP system simulation framework, we demonstrate the effectiveness of the proposed algorithm for a variety of benchmarks for 16 core and 64 core network-on-chip based CMP architectures. Simulation results show consistent energy savings across the board. We present our work as an investigation of the tradeoff between the achievable energy reduction via DVFS when predictions are done using the effective Kalman filter for different performance penalty thresholds.

Investigation of LSTM based prediction for dynamic energy management in chip multiprocessors

“…These methods based on lastlevel cache miss cycles and on non-pipelined stall cycles can be very sensitive to the accuracy of counting misses and stalls. The study in [21] addressed this issue by estimating performance losses due to frequency throttling by using a concept called delayed instruction count (DIC). They used the estimations in a Kalman filtering technique to predict the workload in the next control period and to identify VF pairs that can help reduce energy consumption without violating the performance constraint set by the user.…”

“…We build our work on the performance loss estimation technique proposed in [21] . This technique uses the new concept of delayed instruction count (DIC).…”

“…The study in [21] introduced such a technique to estimate the performance loss and we use it in this paper as well. The technique uses the concept of delayed instructions count (DIC), which is used to derive an equation to calculate dynamically the amount of performance loss (PL) that would be incurred if we were to switch the current VF pair for a given core for the next control period to a throttling VF pair.…”

“…The amount of performance loss is estimated with respect to the reference case, which is always that of the highest frequency. While the details of the derivation are available in [21] , here we only present the final formula that we later use inside the DVFS based energy optimization algorithm. This formula is given by the following expression:…”

“…The method described in [21] proposed a Kalman filtering approach to predict the workload in the next control period. Our objective in this paper is to investigate other prediction approaches.…”