Dynamic SPICE-simulation of the electrothermal behavior of SOI MOSFET's

Bielefeld, J.; Pelz, Georg; Abel, H.; Zimmer, G.

doi:10.1109/16.469405

Cited by 26 publications

(14 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Afterward in the third step, we introduce a simple selfheating model for the transistors, similar to the one proposed by Bielefeld et al [13] to mimic a temperature behavior following the supply voltage wave, its schematic is shown in Fig. 1 (e).…”

Section: Proposed Methodology To Evaluate Criticalmentioning

confidence: 99%

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability

Rosa

Brum

Wirth

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

View full text Add to dashboard Cite

Abstract-FinFET technology appears as an alternative solution to mitigate short-channel effects in traditional CMOS down-scaled technology. Emerging embedded systems are likely to employ FinFET and dynamic voltage scaling (DVS), aiming to improve system performance and energy-efficiency. This paper claims that the use of DVS increases the susceptibility of FinFETbased SRAM cells to soft errors under radiation effects. To investigate that, a methodology that allows determining the critical charge according to the dynamic behaviour of the temperature as a function of the voltage scaling is used. Obtained results support our claim by showing that both temperature and voltage scaling can increase up to five times the susceptibility of FinFET-based SRAM cells to the occurrence of soft errors.

show abstract

Section: Proposed Methodology To Evaluate Criticalmentioning

confidence: 99%

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability

Rosa

Brum

Wirth

et al. 2015

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

View full text Add to dashboard Cite

show abstract

“…In compact models two-dimensional (2-D) heat-flow analysis [35] is too complicated, and it is usually preferred [14], [36] to assume thermal equilibrium and use an average temperature rise . A separate circuit is used to model the thermal behavior of a device [37], [38], consisting of a thermal resistance and a thermal capacitance . Only one time constant has been embedded in the model, but if more are needed [39], a higher order network can be added externally.…”

Section: Modelling Heating Effectsmentioning

confidence: 99%

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

D'Halleweyn

Benson

Redman-White

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias. The device current is described by two main equations handling the MOS channel and the drift region, both of which are smooth and continuous in all operating regimes. Attention is also given to the modeling of inversion at the back oxide to ensure correct behavior is predicted for a source follower in power control applications ("high side operation"). A surface-potential-based formulation is used for the inversion/accumulation channel giving smooth transitions between different regions of operation, and care has been taken to ensure all expressions are smooth and infinitely differentiable to achieve the best possible convergence performance. Self (and coupled) heating effects exert a major influence over the behavior of power SOI devices, and these issues are incorporated in the model core in a consistent fashion.The model has been installed in a commercial SPICE-type circuit simulator and evaluated against individual devices and complete circuits fabricated in an industrial smart power SOI process. Accuracy is significantly improved with respect to the existing LDMOS models, and convergence behavior in switching and linear circuit simulations is comparable with industry standard models of this complexity.

show abstract

“…As an improvement to this method, we introduce a simple self-heating model for the transistors, similar to the one proposed by Bielefeld et al [10]. Its schematic is shown in Fig.…”

Section: Proposed Methodologymentioning

confidence: 99%

Impact of dynamic voltage scaling and thermal factors on SRAM reliability

Rosa

Brum

Wirth

et al. 2015

Microelectronics Reliability

View full text Add to dashboard Cite

This work investigates the e↵ects of temperature and voltage scaling in neutron-induced bit-flip in SRAM memory cells. Proposed approach allows determining the critical charge according to the dynamic behaviour of the temperature as a function of the voltage scaling. Experimental results show that both temperature and voltage scaling can increase in at least two times the susceptibility of SRAM cells to Soft Error Rate (SER). In addition, a model for electrical simulation for soft error and di↵erent voltages was described to investigate the e↵ects observed in the practical neutron irradiation experiments. Results can guide designers to predict soft error e↵ects during the lifetime of SRAM-based devices considering di↵erent power supply modes.

show abstract

Dynamic SPICE-simulation of the electrothermal behavior of SOI MOSFET's

Cited by 26 publications

References 21 publications

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

Impact of dynamic voltage scaling and thermal factors on SRAM reliability

Contact Info

Product

Resources

About